參數(shù)資料
型號： CLC5903SM
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 衰減器
英文描述： Dual Digital Tuner / AGC
中文描述： RF/MICROWAVE DOWN CONVERTER
封裝： BGA-128
文件頁數(shù)： 18/29頁
文件大?。?/td> 698K
代理商： CLC5903SM
www.national.com
18
C
rate of 270.833kHz. An OSP starts when a sample is ready
and stops when the next one is ready.
Serial Outputs
The CLC5903 provides a serial clock (
SCK
), a frame strobe
(
SFS
) and two data lines (
AOUT
and
BOUT
) to output serial
data. The MUX_MODE control register specifies whether the
two channel outputs are transmitted on two separate serial
pins, or multiplexed onto one pin in a time division multi-
plexed (TDM) format. Separate output pins are not provided
for the I and Q halves of complex data. The I and Q outputs
are always multiplexed onto the same serial pin. The I-com-
ponent is output first, followed by the Q-component. By set-
ting the PACKED mode bit to ‘1’ a complex pair may be
treated as a single double-wide word. The
RDY
signal is
used to identify the first word of a complex pair of the TDM
formatted output when the SFS_MODE bit is set to ‘0’. Set-
ting SFS_MODE to ‘1’ causes the CLC5903 to output a sin-
gle
SFS
pulse for each output period. This
SFS
pulse will be
coincident with
RDY
and only a single
SCK
period wide. The
TDM modes are summarized in Table 1.
The serial outputs use the format shown in Figure 30. Figure
30(a) shows the standard output mode (the PACKED mode
bit is low). The chip clocks the frame and data out of the chip
on the rising edge of
SCK
(or falling edge if the SCK_POL bit
in the input control register is set high). Data should be cap-
tured on the falling edge of
SCK
(rising if SCK_POL=1). The
SFS_MODE
MUX_MODE
SERIAL OUTPUTS
AOUT
BOUT
0
0
OUT
A
OUT
B
1
OUT
A
, OUT
B
LOW
1
0
OUT
A
OUT
B
1
OUT
A
, OUT
B
LOW
Table 1. TDM Modes
SCK
SFS
AOUT
I15
I14
I1
I0
Q15
Q14
(a) UNPACKED MODE, FRAME SYNC AT THE START OF EACH WORD
SCK
SFS
AOUT
I15
I14
I1
I0
Q15
Q14
(b) PACKED MODE, ONE FRAME SYNC AT THE START OF EACH DOUBLE-WORD TRANSFER
clock stops and data is zero after transfers are complete
RDY
(c) ONE OR TWO CHANNEL MUX AND SFS MODES (PACKED MODE IS ON)
SFS
AOUT
A
|
BOUT
MUX_MODE=0, SFS_MODE=0|1
MUX_MODE=1, SFS_MODE=0
Output Sample Period (OSP)
Q1
Q0
Q1
Q0
IA
QA
SFS
IA
QA
IB
QB
IA
QA
IB
QB
IA
QA
SCK
SFS
AOUT
mI7
eI3
eI0
eQ3
(d) FLOATING POINT FORMAT
eQ0
mQ0
mI0
mQ7
leading edge of RDY aligns with leading edge of SFS
Figure 30. Serial output formats. Refer to Figure 10 for detailed timing information
RDY is 2 CK periods wide
mI6
eI2
clock stops and data is zero after transfers are complete
clock stops and data is zero after transfers are complete
SFS
AOUT
MUX_MODE=1, SFS_MODE=1
IA
QA
IB
QB
IA
QA
IB
QB
Output Modes
(Continued)
相關PDF資料
PDF描述
CLC5903VLA Dual Digital Tuner / AGC
CLC5955 11-bit, 55MSPS Broadband Monolithic A/D Converter
CLC5955MTDX 11-bit, 55MSPS Broadband Monolithic A/D Converter
CLC5956PCASM 12-bit, 65 MSPS Broadband Monolithic A/D Converter
CLC5956 12-bit, 65 MSPS Broadband Monolithic A/D Converter(12位65 MSPS寬帶單片A/D轉(zhuǎn)換器)
相關代理商/技術參數(shù)
參數(shù)描述
CLC5903SM/NOPB 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128
CLC5903VLA 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128
CLC5903VLA/NOPB 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128
CLC5955 制造商:NSC 制造商全稱:National Semiconductor 功能描述:11-bit, 55MSPS Broadband Monolithic A/D Converter
CLC5955MTD 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述:
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