參數(shù)資料
型號(hào)： CLC5903SM
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 衰減器
英文描述： Dual Digital Tuner / AGC
中文描述： RF/MICROWAVE DOWN CONVERTER
封裝： BGA-128
文件頁(yè)數(shù)： 24/29頁(yè)
文件大小： 698K
代理商： CLC5903SM
www.national.com
24
C
AGC Theory of Operation
A block diagram of the AGC is shown in Figure 34. The
DVGA interface comprises four pins for each of the channels.
The first three pins of this interface are a 3-bit binary word
that controls the
DVGA gain in 6dB steps (
AGAIN
). The final
pin is
ASTROBE
which allows the
AGAIN
bits to be
latched
into the DVGA’s register. A key feature of the
ASTROBE,
illustrated Figure 35, is that it toggles only if the data on
AGAIN
has changed from the previous cycle. Not shown is
that
ASTROBE
and
BSTROBE
are independent. For exam-
ple,
ASTROBE
only toggles when
AGAIN
has changed.
BSTROBE
will not toggle because
AGAIN
has changed.
This is done to minimize unnecessary digital noise on
the
sensitive analog path through the DVGA.
ASTROBE
and
BSTROBE
are asserted during
MR
and
SI
to properly initial-
ize the DVGAs.
The absolute value circuit and the 2-stage, decimate-by-8
CIC filter comprise the power detection part of the AGC. The
power detector bandwidth is set by the CIC filter to F
CK
/8.
The absolute value circuit doubles the effective input fre-
quency. This has the effect of reducing the power detector
bandwidth from F
CK
/8 to F
CK
/16.
For a full-scale sinusoidal input, the absolute value circuit
output is a dc value of
value circuit also generates undesired even harmonic terms,
the CIC filter (response shown in Figure 36), is required to,
remove these harmonics. The first response null occurs at
F
CK
/8, where F
CK
is the clock frequency, and the response
magnitude is at least 25dB below the dc value from F
CK
/10 to
9F
CK
/10. Because the 2
nd
harmonic from the absolute value
. Because the absolute
circuit is about 10dB below the dc this means that the ripple
in the detected level is about 0.7dB or less for input frequen-
cies between F
CK
/20 to 19F
CK
/20. Setting the
AGC_COMB_ORD register to either 1 or 2 will narrow the
power detector’s bandwidth as shown in Figure 36.
The “FIXED TO FLOAT CONVERTER” takes the fixed point
9-bit output from the CIC filter and converts it to a “floating
point” number. This conversion is done so that the 32 values
in the RAM can be uniformly assigned (dB scale) to detected
power levels (54 dB range). This provides a resolution of
1.7dB between detected power levels. The truth table for this
converter is given in Table 3. The upper three bits of the out-
put represent the exponent (e) and the lower 2 are the man-
tissa (m). The exponent is determined by the position of the
AGC_LOOP_GAIN
S
V
A
10
C
T
F
2
3
S
16
5
M
8
12
12
AGC_HOLD_IC
-REF
LOG
FUNCTION PROGRAMMED
INTO RAM
AGC_IC_A
3
AIN[13:4]
(from MUXA)
9
D
C
R
AGC_TABLE
AGAIN
Figure 34. CLC5903 AGC circuit, Channel A
EXP
9
P
C
P
OUT
Figure 35. Timing diagram for AGC/DVGA interface, Channel A. Refer to Figure 9 for detailed timing information.
ASTROBE
AGAIN[2:0]
CK
CK/8
ASTROBE
does not pulse because
AGAIN[2:0]
does not change
511
2
π
(
)
Figure 36. Power detector filter response, 52MHz
0
5
10
15
20
25
30
35
40
45
50
100
90
80
70
60
50
40
30
20
10
0
10
Frequency/MHz
M
AGC Power Detection Filter: Amplitude Response
CIC
CIC + 1tap Comb
CIC + 4tap Comb
AGC_COMB_ORD=2
AGC_COMB_ORD=0
AGC_COMB_ORD=1
AGC Theory of Operation
(Continued)
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