參數(shù)資料
型號(hào)： CLC5903SM
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 衰減器
英文描述： Dual Digital Tuner / AGC
中文描述： RF/MICROWAVE DOWN CONVERTER
封裝： BGA-128
文件頁(yè)數(shù)： 2/29頁(yè)
文件大?。?/td> 698K
代理商： CLC5903SM
www.national.com
2
C
Functional Description
The CLC5903 block diagram is shown in Figure 2. The
CLC5903 contains two identical digital down-conversion
(DDC) circuits. Each DDC accepts an independently clocked
14-bit sample at up to 78MSPS, down converts from a
selected carrier frequency to baseband, decimates the signal
rate by a programmable factor ranging from 32 to 16384, pro-
vides channel filtering, and outputs quadrature symbols.
A crossbar switch enables either of the two inputs or a test
register to be routed to either DDC channel. Flexible channel
filtering is provided by the two programmable decimating FIR
filters. The final filter outputs can be converted to a 12-bit
floating point format or standard two’s complement format.
The output data is available at both serial and parallel ports.
The CLC5903 maintains over 100 dB of spurious free
dynamic range and over 100 dB of out-of-band rejection.
This allows considerable latitude in channel filter partitioning
between the analog and digital domains.
The frequencies, phase offsets, and phase dither of the two
sine/cosine numerically controlled oscillators (NCOs) can be
independently specified. Two sets of coefficient memories
and a crossbar switch allow shared or independent filter
coefficients and bandwidth for each channel. Both channels
share the same decimation ratio and input/output formats.
Each channel has its own AGC circuit for use with narrow-
band radio channels where most of the channel filtering pre-
cedes the ADC. The AGC closes the loop around the
CLC5526 DVGA, compressing the dynamic range of the sig-
nal into the ADC. AGC gain compensation in the CLC5903
removes the DVGA gain steps at the output. The time align-
ment of this gain compensation circuit can be adjusted to
support ADCs with different latencies. The AGC can be con-
figured to operate continuously or set to a fixed gain step.
The two AGC circuits operate independently but share the
same programmed parameters and control signals.
The chip receives configuration and control information over
a microprocessor-compatible bus consisting of an 8-bit data
I/O port, an 8-bit address port, a chip enable strobe, a read
strobe, and a write strobe. The chip’s control registers (8 bits
each) are memory mapped into the 8-bit address space of
the control port. Page select bits allow access to the overlaid
A and B set of FIR coefficients.
JTAG boundary scan and on-chip diagnostic circuits are pro-
vided to simplify system debug and test.
The CLC5903 supports 3.3V I/O even though the core logic
voltage is 1.8V. The CLC5903 outputs swing to the 3.3V rail
so they can be directly connected to 5V TTL inputs if desired.
Figure 2. CLC5903 Dual Digital Tuner / AGC Block Diagram with Control Register Associations
AIN
BIN
MUX
A
MUX
B
Input Source
A_SOURCE
B_SOURCE
Output Controls
RATE
SOUT_EN
SCK_POL
SFS_POL
RDY_POL
MUX_MODE
PACKED
FORMAT
DEBUG_EN
DEBUG_TAP
SFS_MODE
SDC_EN
Output Formatter
Floating Point:
4-bit Exponent and
8-bit Mantissa
or
32-bit Truncated or
24-bit Rounded or
16-bit Rounded or
8-bit Truncated
(see Figure 29)
Two’s Complement:
AOUT/BOUT
BOUT
SCK
SFS
RDY
POUT[15..0]
PSEL[2..0]
POUT_EN
CKA
CKB
CLK
GEN
TEST_REG
Channel B Controls
GAIN_B
PHASE_B
AGC_IC_B AGC_RB_B
FREQ_B
DITH_B
Common Channel Controls
DEC_BY_4
SCALE
EXP_INH
EXT_DELAY
AGC_HOLD_IC
AGC_LOOP_GAIN
AGC_TABLE
AGC_COMB_ORD
PAGE_SEL_F1
F1B_COEFF
PAGE_SEL_F2
F2B_COEFF
AGAIN[2..0]
ASTROBE
BGAIN[2..0]
BSTROBE
Microprocessor
Interface
RD
WR
CE
A[7:0]
D[7:0]
SI
MR
Sync
Logic
14
14
DEC
Channel A
Tuning,
Channel Filters, and
AGC (see Figure 16)
Channel B
Tuning,
Channel Filters, and
AGC (see Figure 16)
SCK_IN
COEF_SEL_F1B
COEF_SEL_F2B
Channel A Controls
GAIN_A
PHASE_A
AGC_IC_A AGC_RB_A
FREQ_A
DITH_A
COEF_SEL_F1A
COEF_SEL_F2A
F1A_COEFF
F2A_COEFF
相關(guān)PDF資料
PDF描述
CLC5903VLA Dual Digital Tuner / AGC
CLC5955 11-bit, 55MSPS Broadband Monolithic A/D Converter
CLC5955MTDX 11-bit, 55MSPS Broadband Monolithic A/D Converter
CLC5956PCASM 12-bit, 65 MSPS Broadband Monolithic A/D Converter
CLC5956 12-bit, 65 MSPS Broadband Monolithic A/D Converter(12位65 MSPS寬帶單片A/D轉(zhuǎn)換器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CLC5903SM/NOPB 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
CLC5903VLA 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
CLC5903VLA/NOPB 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
CLC5955 制造商:NSC 制造商全稱:National Semiconductor 功能描述:11-bit, 55MSPS Broadband Monolithic A/D Converter
CLC5955MTD 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述:
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