參數(shù)資料
型號(hào)： CLC5902
廠商： National Semiconductor Corporation
英文描述： Dual Digital Tuner/AGC
中文描述： 雙數(shù)字調(diào)諧器/自動(dòng)增益控制
文件頁數(shù)： 26/28頁
文件大小： 783K
代理商： CLC5902
Rev. 3.05 May 27, 1999
26
1999 National Semiconductor Corporation
EQ. 9
The term G
L
in this equation is the loop gain,
EQ. 10
The design equations are obtained by solving Equation 9
for G
L
and Equation 10 for
a control register value that determines the number of bits
to shift the output of the RAM down by. This allows some
of the loop gain to be moved out of the RAM so that the
full output range of the table is utilized but not exceeded.
The valid range for AGC_LOOP_GAIN is from 0 to 3
which corresponds to a 1 to 4 bit shift left.
An example set of numbers to implement a loop having a
reference of 6dB below full scale, a deadband of 8dB, and
a loop gain of 0.108 is:
-102 -102 -88 -80 -75 -70 -66
-63 -61 -56 -53 -50
-47 -42 -39 -36 -33 -29 -25
-22 -19 -15 -11 0
0 0 0 0 0 13 17 20
These values are shown plotted in Figure 35 with respect
to the table addresses in (a), and the CIC filter output
P
OUT
in (b). For a 52MHz clock rate and
AGC_LOOP_GAIN=2, these values result in a loop time
constant of
.
1.5
μ
s
. AGC_LOOP_GAIN is
The error signal from the loop gain “SHIFT DOWN” cir-
cuit is gated into the loop integrator. The gate is controlled
by a timing and control circuit discussed in the next para-
graph. A MUX within the integrator feedback allows the
integrator to be initialized to the value loaded into
AGC_IC_A (channel B can be set independently). The
conditions under which it is initialized are configured in
the registers associated with the timing and control circuit.
The top eight bits of the integrator output can also be read
back over the microprocessor interface from the
AGC_RB_A (or AGC_RB_B) register. The top 3 bits
below
the sign become
AGAIN
and are output along with
ASTROBE
signal on the DVGA interface pins. The valid
range of
AGAIN
is from 0 to 7 which corresponds to a
valid range of 0 to 2
10
-1 for the 11-bit, 2’s complement
integrator output from which
AGAIN
is derived. This is
illustrated in Figure 36. The integrator saturates at these
limits to prevent overshoots as the integrator attempts to
enter the valid range. The
AGAIN
value is inverted (
EXP
)
and used to adjust the gain of the incoming signal to pro-
vide a linear output dynamic range. The relationship
between the DVGA analog gain (
AGAIN
) and the
“FIXED TO FLOAT CONVERTER” digital gain (
EXP
) is
shown in Table 7. The DVGA’s compression of the incom-
ing signal in the analog domain vs. the subsequent expan-
sion in the digital domain is shown in Figure 30.
Several control bits allow the user to configure a variety of
AGC algorithms. The AGC may free run by setting
AGC_FORCE high and AGC_HOLD_IC low.
If a burst
start pulse is available and sent to the
AGC_EN
pin, the
τ
F
CK
--8
G
L
--1
1
2
+
.
=
G
L
6.02
S
RAM
2
AGC_LOOP_GAIN
4
–
(
)
.
–
=
S
RAM
0
10
20
30
40
50
60
-120
-100
-80
-60
-40
-20
0
20
0
5
10
15
20
25
30
-120
-100
-80
-60
-40
-20
0
20
ADDRESS
A
P
OUT
(dB)
A
(a)
(b)
Figure 35
Example of programmed RAM contents
0
1x2
7
2x2
7
3x2
7
4x2
7
Integrator Output
5x2
7
6x2
7
7x2
7
8x2
7
0
1
2
3
4
5
6
7
A
The min integrator
For t-1
7
-1
=2
Figure 36
AGC integrator output limits
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