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參數(shù)資料
| 型號(hào)： | CLC5902 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Dual Digital Tuner/AGC |
| 中文描述： | 雙數(shù)字調(diào)諧器/自動(dòng)增益控制 |
| 文件頁(yè)數(shù)： | 24/28頁(yè) |
| 文件大?。?/td> | 783K |
| 代理商： | CLC5902 |
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Rev. 3.05 May 27, 1999
24
1999 National Semiconductor Corporation
A block diagram of the AGC is shown in Figure 32. The
DVGA interface comprises four pins for each of the chan-
nels. The first three pins of this interface are a 3-bit binary
word that controls the
DVGA gain in 6dB steps (
AGAIN
).
The final pin is
ASTROBE
which allows the
AGAIN
bits
to be
latched into the DVGA’s register. A key feature of
the
ASTROBE,
illustrated Figure 33, is that it toggles
only if the data on
AGAIN
has changed from the previous
cycle. Not shown is that
ASTROBE
and
BSTROBE
are
independent. For example,
ASTROBE
should only toggle
when
AGAIN
has changed.
BSTROBE
should not toggle
because
AGAIN
has changed. This is done to minimize
unnecessary digital noise on
the sensitive analog path
through the DVGA.
ASTROBE
and
BSTROBE
are
asserted during
MR
and
SI
to properly initialize the
DVGAs.
The absolute value circuit and the 2-stage, decimate-by-8
CIC filter comprise the power detection part of the AGC.
The power detector bandwidth is set by the CIC filter to
F
CK
/8. The absolute value circuit doubles the effective
input frequency. This has the effect of reducing the power
detector bandwidth from F
CK
/8 to F
CK
/16.
For a full-scale sinusoidal input, the absolute value circuit
output is a dc value of
value circuit also generates undesired even harmonic
terms, the CIC filter (response shown in Figure 34), is
required to remove these harmonics. The first response
null occurs at F
CK
/8, where F
CK
is the clock frequency,
and the response magnitude is at least 25dB below the dc
value from F
CK
/10 to 9F
CK
/10. Because the 2
nd
harmonic
from the absolute value circuit is about 10dB below the dc
this means that the ripple in the detected level is about
0.7dB or less for input frequencies between F
CK
/20 to
19F
CK
/20.
The “FIXED TO FLOAT CONVERTER” takes the fixed
point 9-bit output from the CIC filter and converts it to a
“floating point” number. This conversion is done so that
the 32 values in the RAM can be uniformly assigned (dB
. Because the absolute
AGC Theory of Operation
AGC_LOOP_GAIN
S
V
A
10
C
T
F
2
3
S
16
5
M
8
12
12
PERIOD
LOAD
EN
16
C
O
AGC_FORCE
AGC_HOLD_IC
-REF
LOG
FUNCTION PROGRAMMED
INTO RAM
AGC_EN
AGC_COUNT
AGC_IC_A
3
AIN[13:4]
9
D
C
R
P
OUT
AGC_RESET_EN
AGC_TABLE
AGAIN
Figure 32
CLC5902 AGC circuit, Channel A
EXP
ASTROBE
AGAIN[2:0]
CK
CK/8
1
SCK
delay
ASTROBE
does not pulse because
AGAIN[2:0]
does not change
Figure 33
Timing diagram for AGC/DVGA interface, Channel A. Refer to Figure 8 for detailed timing information.
511
2
π
(
)
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| CLC5903SM | 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| CLC5903SM/NOPB | 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
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