參數(shù)資料
型號(hào)： CLC5902
廠商： National Semiconductor Corporation
英文描述： Dual Digital Tuner/AGC
中文描述： 雙數(shù)字調(diào)諧器/自動(dòng)增益控制
文件頁(yè)數(shù)： 21/28頁(yè)
文件大?。?/td> 783K
代理商： CLC5902
1999 National Semiconductor Corporation
21
Rev. 3.05 May 27, 1999
Test and Diagnostics
The CLC5902 supports IEEE 1149.1 compliant JTAG
Boundary Scan for the I/O’s. The following pins are used:
TRST (test reset)
TMS
(test mode select)
TDI
(test data in)
TDO
(test data out)
TCK
(test clock)
The following JTAG instructions are supported:
The JTAG Boundary Scan can be used to verify printed
circuit board continuity at the system level.
The user is able to program a value into TEST_REG and
substitute this for the normal channel inputs from the
AIN/
BIN
pins by selecting it with the crossbar. With the NCO
frequency set to zero this allows the DDCs and the output
interface of the chip to be verified. Also, the AGC loop
can be opened by setting AGC_HOLD_IC high and set-
ting the gain of the DVGA by programming the appropri-
ate value into the AGC_IC_A/B register.
Real-time access to the following signals is provided by
configuring the control interface debug register:
NCO sine and cosine outputs
data after round following mixers
data before F1 and F2
data after the CIC filter within the AGC
The access points are multiplexed to a 20-bit parallel out-
put port which is created from signal pins
POUT[15:0]
,
AOUT
,
BOUT
,
SFS
, and
RDY
according to the table
below:
SCK
will be set
to the proper strobe rate for each debug
tap point.
POUT_EN
and
PSEL[2..0]
have no effect in
Debug Mode. The outputs are turned on when the Debug
Mode bit is set. Normal serial outputs are also disabled.
Control Registers
The chip is configured and controlled through the use of 8-
bit control registers. These registers are accessed
for read-
ing or writing using the control bus pins (CE, RD, WR,
A[7:0], and D[7:0]) described in the Control Interface sec-
tion. The register names and descriptions are listed in
Table 5.
Instruction
Description
BYPASS
Connects TDI directly to TDO
EXTEST
Drives the ‘extest’ TAP controller output
IDCODE
Connects the 32-bit ID register to TDO
SAMPLE/PRELOAD
Drives the ‘samp_load’ TAP controller output
HIGHZ
Tri-states the outputs
Normal Mode Pin
Debug Mode Pin
POUT[15:0]
DEBUG[19..4]
RDY
DEBUG[3]
SFS
DEBUG[2]
AOUT
DEBUG[1]
BOUT
DEBUG[0]
Register Name
Width
Type
Default
a
Addr
Bit
Description
DEC
11b
R/W
7
0(LSBs)
1(MSBs)
7:0
2:0
CIC decimation control. N=DEC+1. Valid range is from 7 to 2047. Format is an unsigned
integer. This affects both channels.
DEC_BY_4
1b
R/W
0
1
4
Controls the decimation factor in F2. 0=Decimate by 2. 1=Decimate by 4. This affects both
channels.
SCALE
6b
R/W
0
2
5:0
CIC SCALE parameter. Format is an unsigned integer representing the number of left bit
shifts to perform on the data prior to the CIC filter. Valid range is from 0 to 40. This affects
both channels.
GAIN_A
3b
R/W
0
3
2:0
Value of left bit shift prior to F1 for channel A.
GAIN_B
3b
R/W
0
4
2:0
Value of left bit shift prior to F1 for channel B.
RATE
1B
R/W
1
5
7:0
Determines rate of serial output clock. The output rate is FCK/(RATE+1). Unsigned integer.
SOUT_EN
1b
R/W
0
6
0
Enables the serial output pins
AOUT
,
BOUT
,
SCK
, and
SFS
. 0=Tristate. 1=Enabled.
SCK_POL
1b
R/W
0
6
1
Determines polarity of the
SCK
output. 0=
AOUT
,
BOUT
, and
SFS
change on the rising edge
of SCK (capture on falling edge). 1=They change on the falling edge of SCK.
SFS_POL
1b
R/W
0
6
2
Determines polarity of the
SFS
output. 0=Active High. 1=Active Low.
RDY_POL
1b
R/W
0
6
3
Determines polarity of the
RDY
output. 0=Active High. 1=Active Low.
MUX_MODE
1b
R/W
0
6
4
Determines the mode of the serial outputs. 0=Each channel is output on its respective pin,
1=Both channels are multiplexed and output on
AOUT
. See also Table 2.
PACKED
1b
R/W
0
6
5
Controls when
SFS
goes active. 0=
SFS
pulses prior to the start of the I and the Q words.
1=
SFS
pulses only once prior to the start of each I/Q sample pair (i.e. the pair is treated as a
double-sized word) The I word precedes the Q word. See Figure 29.
FORMAT
2b
R/W
0
6
6:7
Determines output number format. 0=Truncate serial output to 8 bits. Parallel output is trun-
cated to 32 bits. 1=Round both serial and parallel to 16 bits. All other bits are set to 0.
2=Round both serial and parallel to 24 bits. All other bits are set to 0. 3=Output floating point.
8-bit mantissa, 4-bit exponent. All other bits are set to 0.
Table 5
CLC5902 Control Registers
Control Registers
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