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參數(shù)資料
| 型號： | CLC408AJE-TR13 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運動控制電子 |
| 英文描述： | Comlinear CLC408 High-Speed, Low-Power Line Driver |
| 中文描述： | OP-AMP, 11000 uV OFFSET-MAX, PDSO8 |
| 封裝： | 0.150 INCH, PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大小： | 199K |
| 代理商： | CLC408AJE-TR13 |
5
http://www.national.com
CLC408 DESIGN INFORMATION
Standard op amp circuits work with CFB op amps.
There are 3 unique design considerations for CFB:
I
The feedback resistor (R
f
in Figures 1-3) sets
AC performance
I
R
f
cannot be replaced with a short or a capacitor
I
The output offset voltage is not reduced by
balancing input resistances
The following sub-sections cover:
I
Design parameters, formulas and techniques
I
Interfaces
I
Application circuits
I
Layout techniques
I
SPICE model information
DC Gain (non-inverting)
The non-inverting DC voltage gain for the configuration
shown in Figure 1 is:
Figure 1: Non-Inverting Gain
The normalized gain plots in the
Typical Performance
Characteristics
section show different feedback
resistors (R
f
) for different gains. These values of R
f
are
recommended for obtaining the highest bandwidth with
minimal peaking. The resistor R
t
provides DC bias for
the non-inverting input.
For A
v
< 6, use linear interpolation on the nearest A
v
values to calculate the recommended value of R
f
. For
A
v
≥
6, the minimum recommended R
f
is 200
.
Select R
g
to set the DC gain:
DC gain accuracy is usually limited by the tolerance of
R
f
and R
g
.
DC Gain (unity gain buffer)
The recommended R
f
for unity gain buffers is 3k
. R
g
is left open. Parasitic capacitance at the inverting node
may require a slight increase of R
f
to maintain a flat
frequency response.
DC Gain (inverting)
The inverting DC voltage gain for the configuration
shown in Figure 2 is:
The normalized gain plots in the
Typical Performance
Characteristics
section show different feedback
resistors (R
f
) for different gains. These values of R
f
are
recommended for obtaining the highest bandwidth with
minimal peaking. The resistor R
t
provides DC bias for
the non-inverting input.
For |A
v
| < 6, use linear interpolation on the nearest A
v
values to calculate the recommended value of R
f
. For
|A
v
|
≥
6, the minimum recommended R
f
is 200
.
Figure 2: Inverting Gain
Select R
g
to set the DC gain: . At large gains,
R
g
becomes small and will load the previous stage.
This can be solved by driving R
g
with a low impedance
buffer like the CLC111, or increasing R
f
and R
g
. See
the
AC Design (small signal bandwidth)
sub-section
for the tradeoffs.
DC gain accuracy is usually limited by the tolerance of
R
f
and R
g
.
DC Gain (transimpedance)
Figure 3 shows a transimpedance circuit where the
current I
in
is injected at the inverting node. The current
source’s output resistance is much greater than R
f
.
The DC transimpedance gain is:
The recommended R
f
is 3k
. Parasitic capacitance at
the inverting node may require a slight increase of R
f
to
maintain a flat frequency response.
DC gain accuracy is usually limited by the tolerance
of R
f
.
+
CLC408
-
R
f
0.1
μ
F
6.8
μ
F
+
V
o
V
in
V
CC
0.1
μ
F
6.8
μ
F
V
EE
3
2
4
7
6
+
R
g
R
t
A
1
R
R
v
f
g
= +
R
R
A
1
g
f
v
=
A
R
R
v
f
g
=
+
CLC408
-
R
f
0.1
μ
F
6.8
μ
F
+
V
o
V
in
V
CC
0.1
μ
F
6.8
μ
F
V
EE
R
g
R
t
3
2
4
7
6
+
R
R
A
v
A
V
I
in
R
R
o
f
=
=
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