參數(shù)資料
型號(hào)： CLC021
廠(chǎng)商： National Semiconductor Corporation
英文描述： SMPTE 259M Digital Video Serializer with EDH Generation/Insertion(SMPTE 259M數(shù)字視頻串行器帶EDH發(fā)生/插入)
中文描述： 符合SMPTE 259M數(shù)字視頻串行器，帶有增強(qiáng)型擴(kuò)張管代/插入（符合SMPTE 259M數(shù)字視頻串行器帶硬腦膜外血腫發(fā)生/插入）
文件頁(yè)數(shù)： 7/16頁(yè)
文件大?。?/td> 354K
代理商： CLC021
Device Operation
(Continued)
dards: SMPTE 125M, SMPTE 267M, SMPTE 244M or
ITU-R BT.601. If the data is 8-bit, it is converted to a 10-bit
representation according to the type of data being input:
component 4:2:2 per SMPTE 259M paragraph 7.1.1, com-
posite NTSC per paragraph 8.1.1 or composite PAL per
paragraph 9.1.1. Eight-bit video data corresponds to the up-
per 8 bits of the 10-bit video data word and is MSB-aligned.
Output from this register feeds the TRS (sync) character de-
tector, SMPTE polynomial generator/serializer and the EDH
polynomial generators/serializers and control system. All
parallel data and clock inputs have internal pull-down de-
vices.
The
sync detector
or TRS character detector receives data
from the input register. The detection function is controlled
by Sync Detect Enable, a low-true, TTL-compatible, external
signal. Synchronization words, the timing reference signals
(TRS), start-of-active-video (SAV) and end-of-active-video
(EAV) are defined in SMPTE 125M and 244M. The sync de-
tector supplies control signals to the SMPTE polynomial
generator to identify the presence of valid video data, and to
the EDH control block. In SMPTE mode, TRS character
LSB-clipping as prescribed in ITU-R BT.601 is enabled. LSB-
clipping causes all TRS characters with a value between
000h and 003h to be forced to 000h and all TRS characters
with a value between 3FCh and 3FFh to be forced to 3FFh.
Clipping is done prior to encoding or EDH character genera-
tion. This function is disabled in non-SMPTE mode opera-
tion.
Outputs from the sync detector are:
1.
H, V, and F or Line/Field ID
—For component video,
these are registered outputs corresponding to input TRS
data bits 6, 7 and 8, respectively. These outputs are dis-
abled in non-SMPTE mode. The outputs are active
HIGH-true. For composite video, these outputs corre-
spond to the line and field ID encoded as input parallel
data bits 2 (MSB) through 0. These outputs are regis-
tered for the duration of the applicable field.
2.
NSP
—New Sync Position: A function and output indi-
cating that a new or out-of-place TRS character has
been detected. This output remains active for at least
one horizontal line period (reset by EAV) or unless re-
activated by a subsequent new or out-of-place TRS. Ac-
tivation of this function flushes the existing state of the
machine reseting the EDH generator, SMPTE polyno-
mial generator, serializer and NRZ-NRZI converter. This
function is disabled in non-SMPTE mode operation. The
output is active HIGH-true.
3.
ANC
—Ancilliary data location output: Indicates that the
ancilliary data header (component) or flag (composite)
has been detected. The output is a pulse having a dura-
tion of one P
CLK
period. The output is active HIGH-true.
SMPTE POLYNOMIAL GENERATOR AND CONTROLS
The
SMPTE Mode
input allows the CLC021 to function both
as a full SMPTE 259M encoder or general-purpose 8- or 10-
bit serializer. SMPTE mode is enabled when this input is
LOW. Non-SMPTE mode is enabled when this pin is HIGH.
This pin is pulled internally to V
when unconnected. When
in SMPTE mode, the SMPTE polynomial generator; TRS
sync detection circuitry; EDH control circuitry; H, V, F and
NSP outputs and TRS clipping are enabled.
The
SMPTE polynomial generator
accepts the parallel
video data and encodes it using the polynomial X
9
+ X
4
+ 1
as specified in SMPTE 259M (1997 rev.), paragraph 5 and
Annex C. The transmission bit order is LSB-first, per para-
graph 6.
NRZ-TO-NRZI CONVERTER
The
NRZ-to-NRZI converter
accepts NRZ serial data from
the SMPTE and EDH polynomial genertors and converts it to
NRZI using the polynomial (X + 1) per SMPTE 259M, para-
graph 5.2 and Annex C. The converter’s output goes to the
output buffer amplifier. The
NRZ/NRZI input
enables this
conversion function. Conversion from NRZ to NRZI is en-
abled when the input is a logic LOW. Conversion to NRZI is
disabled when this input is a logic-HIGH. This function is not
affected by the SMPTE mode control input. The input pin is
pulled internally to V
SS
(NRZI enabled) when unconnected.
EDH SYSTEM OPERATION
The CLC021 has EDH character and flag generation and in-
sertion circuitry which operates as proposed in SMPTE RP-
165. Inputs and circuitry are provided to control generation
and automatic insertion of the EDH check words at proper lo-
cations in the serial data output.
The
EDH polynomial generators
accept parallel data from
the input register and generate 16-bit serial check words us-
ing the polynomial X
16
+ X
12
+ X
6
+ 1. Separate calculations
are made for each video field prior to serialization. Separate
CRCs for the full-field and active picture along with status
flags are inserted and serially transmitted with the other
data. Upon being reset, the initial state of all EDH check
characters is 00h.
The
EDH control
system accepts input from the sync detec-
tor and controls the EDH polynomial generator and SMPTE/
EDH polynomial insertion multiplexer.
EDH Enable
, an ex-
ternal TTL-compatible, low-true input, enables this circuitry.
The controller inserts the EDH check words in the serial data
stream at the correct positions in the ancilliary data space
per SMPTE 259M paragraph 7.3, 8.4.4 or 9.4.4 and per
SMPTE RP-165. Ancilliary data space is formatted per
SMPTE 291M.
The
EDH Force
control input causes the insertion of new
EDH checkwords and flags into the serial output regardless
of the previous condition of EDH checkwords and flags in the
input parallel data. This function may be used in situations
where video content has been editted thus making the previ-
ous EDH information invalid.
The
NTSC/PAL
output indicates the type of component or
composite data standard being input to the CLC021. This
output is useful for troubleshooting or may be used to drive a
panel indicator. The output is high when 625-line PAL data is
being input and low when 525-line NTSC data is being input.
PHASE-LOCKED LOOP AND VCO
The
phase-locked loop
(PLL) system generates the output
serial data clock at 10x the parallel data clock frequency.
This
system
consists
of
phase-frequency detector and internal loop filter. The VCO
free-running frequency is internally set. The PLL automati-
cally generates the appropriate frequency for the serial clock
rate using the parallel data clock (P
) frequency as its ref-
erence. Loop filtering is internal to the CLC021. The VCO
has separate V
and V
power supply feeds, pins 27
and 28, which may be supplied power via an external low-
pass filter, if desired. The PLL acquisition (lock) time is less
than 75 μs
@
270 Mbps. The VCO halts when no P
CLK
signal
is present or is inactive.
a
VCO,
divider
chain,
C
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7
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