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參數(shù)資料
| 型號： | CLC021 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | SMPTE 259M Digital Video Serializer with EDH Generation/Insertion(SMPTE 259M數(shù)字視頻串行器帶EDH發(fā)生/插入) |
| 中文描述： | 符合SMPTE 259M數(shù)字視頻串行器，帶有增強型擴張管代/插入（符合SMPTE 259M數(shù)字視頻串行器帶硬腦膜外血腫發(fā)生/插入） |
| 文件頁數(shù)： | 14/16頁 |
| 文件大小： | 354K |
| 代理商： | CLC021 |
Application Information
(Continued)
The jitter test setup used to obtain values quoted in the data
sheet consists of:
National Semiconductor SD021-5EVK (SD021-3EVK),
CLC021 evaluation kit
Tektronix TG2000 signal generation platform with DVG1
option
Tektronix VM700T Option 1S Video Measurement Set
Tektronix TDS 794D, Option C2 oscilloscope
Tektronix P6339A passive probe
75
coaxial cable, 3 ft., Belden 8281 or RG59 (2 re-
quired)
ECL-to-TTL/CMOS
level
Figure 9).
Apply the black-burst reference clock from the TG2000 sig-
nal generator’s BG1 module 27 MHz clock output to the level
converter input. The clock amplitude converter schematic is
shown in Figure 9Adjust the input bias control to give a 50%
duty cycle output as measured on the oscilloscope/probe
system. Connect the level translator to the SD021EVK
board, connector P1, P
CLK
pins (the outer-most row of pins
converter/amplifier,
(see
is ground). Configure the SD021EVK to operate in the NTSC
colour bars, BIST mode. Configure the VM700T to make the
jitter measurement in the jitter FFT mode at the frame rate
with 1 kHz filter bandwidth and Hanning window. Configure
the setup as shown in Figure 8 Switch the test equipment on
(from standby mode) and allow all equipment temperatures
stabilize per manufacturer’s recommendation. Measure the
jitter value after allowing the instrument’s reading to stabilize
(about 1 minute). Consult the VM700T Video Measurement
Set Option 1S Serial Digital Measurements User Manual
(document number 071-0074-00) for details of equipment
operation.
The VM700T measurement system’s jitter floor specification
at 270 Mbps is given as 200 ps
±
20% (100 ps
±
5% typical)
of actual components from 50 Hz to 1 MHz and 200 ps
+60%, -30% of actual components from 1 MHz to 10 MHz.
To obtain the actual residual jitter of the CLC021, a root-sum-
square adjustment of the jitter reading must be made to com-
pensate for the measurement system’s jitter floor specifica-
tion. For example, if the jitter reading is 250 ps, the CLC021
residual jitter is the square root of (250
2
200
2
) = 150 ps.
The accuracy limits of the reading as given above apply.
DS101368-10
FIGURE 8. Jitter Test Circuit
DS101368-13
FIGURE 9. ECL-to-TTL/CMOS Level Converter/Amplifer
C
www.national.com
14
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| CLC021AVGZ-3.3 | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
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