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參數(shù)資料
| 型號： | CLC021 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | SMPTE 259M Digital Video Serializer with EDH Generation/Insertion(SMPTE 259M數(shù)字視頻串行器帶EDH發(fā)生/插入) |
| 中文描述： | 符合SMPTE 259M數(shù)字視頻串行器，帶有增強(qiáng)型擴(kuò)張管代/插入（符合SMPTE 259M數(shù)字視頻串行器帶硬腦膜外血腫發(fā)生/插入） |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 354K |
| 代理商： | CLC021 |
DC Electrical Characteristics—CLC021VGZ-3.3
(Continued)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3).
Symbol
Parameter
Conditions
V
SDO
Serial Driver Output
Voltage
R
REF
= 1.69 k
1%,
Figure 2
I
DD
Power Supply Current,
Total
R
REF
= 1.69 k
1%,
P
CLK
= 27 MHz, NTSC
Colour Bar Pattern,
Figure 2
Reference
SDO, SDO
Min
Typ
Max
Units
R
L
= 75
1%,
720
800
880
mV
P-P
R
L
= 75
1%,
47
mA
AC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3).
Symbol
Parameter
BR
SDO
Serial Data Rate
(Note 5)
t
j
Serial Output Jitter
270 Mbps,Figure 2 (Note 6)
t
jit
Serial Output Jitter
(Notes 4, 5)
t
r
, t
f
Rise Time, Fall Time
20%–80%, (Notes 4, 5)
Output Overshoot
(Note 4)
t
LOCK
Lock Time
(Notes 5, 7)
t
SU
Setup Time
Figure 3 (Note 4)
t
HLD
Hold Time
Figure 3 (Note 4)
L
GEN
Output Inductance
(Note 4)
R
GEN
Output Resistance
(Note 4)
Conditions
Reference
SDO, SDO
SDO, SDO
SDO, SDO
SDO, SDO
SDO, SDO
Min
100
Typ
Max
400
Units
Mbps
ps
P-P
ps
P-P
ps
%
μs
ns
ns
nH
220
100
800
1
75
2
2
6
25k
200
1500
500
D
N
to P
CLK
D
N
from P
CLK
SDO, SDO
SDO, SDO
3
3
Note 1:
“Absolute Maximum Ratings” are those parameter values beyond which the life and operation of the device cannot be guaranteed. The stating herein of
these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of “Electrical Characteristics” speci-
fies acceptable device operating conditions.
Note 2:
Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated referenced to V
SS
= 0V.
Note 3:
Typical values are stated for V
DD
= +5.0V (CLC021VGZ-5.0) or +3.3V (CLC021VGZ-3.3) and T
A
= +25C.
Note 4:
Specification is guaranteed by design.
Note 5:
R
L
= 75
, AC-coupled
@
270 M
bps
, R
REF
= 1.69 k
1%, See Test Loads and Figure 2
Note 6:
CLC021 mounted in the SD021EVK board, configured in BIST mode (NTSC colour bars) with P
CLK
= 27 MHz derived from Tektronix TG2000 black-burst
reference. Timing jitter measured with Tektronix VM700T using jitter measurement FFT mode, frame rate, 1 kHz filter bandwidth, Hanning window.
Note 7:
Measured from rising-edge of first P
CLK
cycle until Lock Detect output goes high (true).
Test Loads
DS101368-3
FIGURE 1. Test Loads
C
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| CLC021AVGZ-3.3 | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
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