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參數(shù)資料
| 型號： | CLC021 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | SMPTE 259M Digital Video Serializer with EDH Generation/Insertion(SMPTE 259M數(shù)字視頻串行器帶EDH發(fā)生/插入) |
| 中文描述： | 符合SMPTE 259M數(shù)字視頻串行器，帶有增強型擴張管代/插入（符合SMPTE 259M數(shù)字視頻串行器帶硬腦膜外血腫發(fā)生/插入） |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 354K |
| 代理商： | CLC021 |
Application Information
(Continued)
APPLICATION CIRCUIT
The SD021EVK application circuit boards, Figure 7 can ac-
commodate different input and output drive and loading op-
tions. Pin headers are provided for input and control I/O sig-
nal access. Install the appropriate value resistor packs,
220
at RP1 and RP3 and 330
at RP2 and RP4, for TTL
cabled interfaces before applying input signals. Install 51
resistor packs at RP2 and RP4 for signal sources requiring
such loading. Remove any resistor packs at RP1 and RP3
when using 50
source loading.
The board’s outputs may be DC interfaced to PECLinputs by
first installing 124
resistors at R1B and R2B, changing R1A
and R2A to 187
and replacing C1 and C2 with short cir-
cuits. The PECL inputs should be directly connected to J1
and J2 without cabling. If 75
cabling is used to connect the
CLC021 to the PECL inputs, the voltage dividers used on the
CLC021 outputs must be removed and re-installed on the
circuit board where the PECL device is mounted. This will
provide correct termination for the cable and biasing for both
the CLC021’s outputs and the PECL inputs. It is most impor-
tant to note that a 75
or equivalent DC loading (measured
with respect to the negative supply rail) must always be in-
stalled at both of the CLC021’s SDO outputs to obtain proper
signal levels from device. When using 75
Thevenin-
equivalent load circuits, the DC bias applied to the SDO out-
puts should not exceed +3V (+1.3V for CLC021VGZ-3.3)
with respect to the negative supply rail. Serial output levels
should be reduced to 400 mV
by changing R
to 3.4 k
.
This may be done by removing the Output Level shorting
jumper on the post header.
The Test Out output is intended for monitoring by equipment
having high impedance test loading (
>
500
). If the Lock De-
tect output is to be externally monitored, the attached moni-
toring circuit should present a DC resistance greater than
5 k
so as not to affect Lock Detect indicator operation.
DS101368-8
FIGURE 6. Typical Application Circuit
C
www.national.com
12
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| CLC021AVGZ-3.3 | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
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