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參數(shù)資料
| 型號： | CLC-CAPT-PCASM |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 763K |
| 代理商： | CLC-CAPT-PCASM |
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Histogram Mode
In the second mode of operation, the
“
Histogram
”
mode,
the data capture board operates as a hardware histo-
grammer. The board does not collect a contiguous record
from the ADC; instead, it compiles statistical information
by counting the number of times that the ADC
outputs each code. The most signi
fi
cant 15 bits of the
converter de
fi
ne 32K histogram bins. The MSB of the
data is inverted before being stored (all data is treated as
offset binary format). ADC data is aligned to the least
signi
fi
cant bit, and unused higher bits are set to 0s. Each
bin is cleared initially. The ADC output code is used as
the address for the SRAM on the board, and as each
code is read by the Data Capture board, the data at that
location in the SRAM is read, incremented and written
back to the SRAM. This counting requires multiple clock
cycles, so the data is not counted in real time. In fact, 11
samples of data are missed for each sample that is
counted. The histogram capture terminates when a bin
reaches the count speci
fi
ed by DIP switches 4 and 5. The
32K histogram bin counts are then returned via the serial
port. If the input signal to the ADC is a pure
sinusoid, then the histogram information can be
compared to the theoretical probability density of a
sinusoid and the linearity of the ADC can be calculated.
The supplied Matlab script DNL_INL uses this method.
Please refer to the IEEE Standard for Digitizing Waveform
Recorders (IEEE Std 1057-1994) for more information
about this technique.
Hardware Con
fi
guration
Jumpers
The data capture board has 2 jumpers that must be
con
fi
gured before use. The
fi
rst jumper, WCLK, selects
the clock source for the FIFO. When capturing data from
an ADC evaluation board,
RDY2
. This selects the DR (Data Ready) clock line from
the ADC evaluation board pin 20B. The second jumper,
VCCD, sets the supply voltage for the ADC output buff-
ers. Unless the ADC evaluation board instructions specify
otherwise, this jumper should be set to +5.
WCLK should be set to
Data Capture Board Block Diagram
DIP Switches
Five of the eight DIP switches are used to con
fi
gure
several capture functions as follows.
DIP switch 1:
Diversity Receiver Evaluation Board or an
ADC Evaluation Board is attached to the Data
Capture Board.
ON
→
ADC Evaluation Board is attached.
Captured data is aligned to the least signi
fi
cant
bit with unused higher bits set to 0s.
This DIP switch speci
fi
es whether a
DIP switches 2 and 3:
indicate that an ADC Evaluation Board is attached,
DIP switches 2 and 3 specify the width of the ADC
data so it can be aligned to the least signi
fi
cant bit
and unused higher bits can be set to 0s.
When DIP switch 1 is ON to
DIP switches 4 and 5:
maximum histogram bin count. The histogram
capture terminates when any bin reaches the count
speci
fi
ed by these switches.
These DIP switches specify the
A maximum count of 16384 corresponds to approxi-
mately 2.5 million total samples for a 12-Bit ADC. The
capture is very fast (on the order of 1 second for a 52
MSPS clock rate) so there is not much advantage in set-
ting the switches for a lower maximum count. The other
settings are more useful for the DRCS evaluations
because the effective clock rate can become very low
with certain output formats and decimation ratios.
CLC5956 Data
Analog Input
Ain- >> Ain
Ain- > Ain
Ain > Ain-
Ain >> Ain-
CLC5958 Data
Analog Input
Ain- >> Ain
Ain- > Ain
Ain > Ain-
Ain >> Ain-
Condition
- Full Scale
- Mid Scale
+ Mid Scale
+ Full Scale
Offset Binary Number
0000 0000 0000
0111 1111 1111
1000 0000 0000
1111 1111 1111
Two's Complement
1000 0000 0000
1111 1111 1111
0000 0000 0000
1111 1111 1111
ASCII Value Stored
2048
4095
0
2047
Condition
- Full Scale
- Mid Scale
+ Mid Scale
+ Full Scale
Offset Binary Number
00 0000 0000 0000
01 0111 1111 1111
10 0000 0000 0000
11 1111 1111 1111
Two's Complement
10 0000 0000 0000
11 1111 1111 1111
00 0000 0000 0000
01 1111 1111 1111
ASCII Value Stored
8192
16383
0
8191
FPGA Performs:
State Machine
Signal Format Conversion
Data Routing
Data
12-18
Bits
J1
Eurocard
Connector
FPGA
SRAM
24-bits
32k depth
FIFO
18-bits
32k depth
UART
J9
9-pin
Serial Cable
Connector
24
Serialized
Data Stream
Note:
Primary data path shown.
Control lines not shown
RDY2
WCLK
Clock
Switch:
2
OFF
OFF
ON
ON
3
OFF
ON
OFF
ON
Number of Bits in ADC
18
16
14
12
Switch:
4
OFF
OFF
ON
ON
5
OFF
ON
OFF
ON
Maximum Count
16384
8192
4096
2048
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