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參數(shù)資料
| 型號(hào)： | CE77 |
| 廠商： | Fujitsu Limited |
| 英文描述： | Semicustom CMOS Embedded array |
| 中文描述： | 半定制嵌入式陣列的CMOS |
| 文件頁數(shù)： | 19/24頁 |
| 文件大?。?/td> | 167K |
| 代理商： | CE77 |
CE77 Series
19
■
AC CHARACTERISTICS
*1 : Delay time
=
propagation delay time, enable time, disable time
*2 : “typ” is calculated from the cell specification.
*3 : Measurement condition
Note : tpd Max is calculated according to the maximum junction temperature (T
j
) .
■
INPUT/OUTPUT CAPACITANCE
■
DESIGN METHOD
Linking a floor plan tool and a logic synthesis tool enables automatic circuit optimization using floor plan infor-
mation. In addition, CDDM (Clock Driven Design Method) clock tree synthesis tools using floor plan information
is also available. Using floor plan information at a pre-layout stage prevents major problems with setup and hold
timings which can occur after layout. Using a hierarchical layout method to support larger-scale circuit design
considerably shortens the overall design cycle time.
(V
DD
=
1.8 V
±
0.15 V, V
SS
=
0 V, T
j
=
40
°
C to
+
125
°
C)
Value
Parameter
Symbol
Unit
Min
Typ
Max
Delay time
t
pd
*
1
typ*
2
×
tmin*
3
typ*
2
×
ttyp*
3
typ*
2
×
tmax*
3
ns
Measurement condition
tmin
ttyp
tmax
V
DD
=
2.5V
±
0.2 V, V
SS
=
0 V, T
j
=
40
°
C to
+
125
°
C
V
DD
=
1.8V
±
0.15 V, V
SS
=
0 V, T
j
=
40
°
C to
+
125
°
C
V
DD
=
1.5V
±
0.1 V, V
SS
=
0 V, T
j
=
40
°
C to
+
125
°
C
0.60
1.00
1.64
0.84
1.57
2.84
1.14
2.22
4.09
(f
=
1 MHz, V
DD
=
V
I
=
0 V, Tj
=
+
25
°
C)
Value
Parameter
Symbol
Unit
Input pin
C
IN
Max 16
pF
Output pin
C
OUT
Max 16
pF
Input/output capacitance
C
I
/
O
Max 16
pF
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