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參數(shù)資料
| 型號： | CDC930DL |
| 英文描述： | CPU SYSTEM CLOCK GENERATOR|SSOP|56PIN|PLASTIC |
| 中文描述： | CPU系統(tǒng)時鐘發(fā)生器| SSOP封裝| 56PIN |塑料 |
| 文件頁數(shù)： | 3/17頁 |
| 文件大小： | 240K |
| 代理商： | CDC930DL |
CDC930
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JULY 2000
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
25
3V48(0)/SelA
I/O
Dual function 3.3 V, Type 3, 48-MHz clock output that latches the state of SelA during power up
3V48(1)/SelB
26
I/O
Dual function 3.3 V, Type 3, 48-MHz clock output that latches the state of SelB during power up
3V66[0–3]
30, 31, 34, 35
O
3.3 V, Type 5, 66-MHz clock outputs
3VMREF
55
O
3.3 V, Type 5, 50/66-MHz memory clock output
3.3 V, Type 5, 50/66-MHz memory clock output (180
°
out of phase with 3VMREF)
Ground for core and HCLK/HCLK, 3VMREF/3VMREF, 3V48, 3V66 and PCI outputs
3VMREF
54
O
GND
1, 7, 13, 19,
24, 32, 33, 37,
40, 46, 53
HCLK[1–4]
42, 45, 48, 51
O
Type X1, host clock outputs
HCLK[1–4]
41, 44, 47, 50
O
Type X1, host complementary clock outputs
I_REF
39
Special
Current reference pin for the host clock pairs. I_REF uses a fixed precision resistor tied to ground
to establish the appropriate current.
PCI[0–9]
8, 9, 11, 12,
14, 15, 17, 18,
20, 21
O
3.3 V, Type 5, 33-MHz PCI clock outputs
PWRDWN
28
I
Power down for complete device with HOST at 2
×
IREF, HCLK not driven and all other outputs
forced low.
REF0/MultSel0
2
I/O
Dual function 3.3 V, Type 3, 14.318-MHz reference clock output. The state of MultSel0 is latched
during power up. MultSel0 configures the IOH amplitude (and thus the VOH swing amplitude) of
the HCLK pair outputs.
REF1/MultSel1
3
I/O
Dual function 3.3 V, Type 3, 14.318-MHz reference clock output. The state of MultSel1 is latched
during power up. MultSel1 configures the IOH amplitude (and thus the VOH swing amplitude) of
the HCLK pair outputs.
SEL100/133
23
I
Active low LVTTL level logic select. SEL100/133 is used for enabling 100/133 MHz. Low=100
MHz, high=133 MHz
SPREAD
52
I
LVTTL level logic select. SPREAD pin enables/disables the spread spectrum for the
HCLK/HCLK, 3VMREF/3VMREF, 3V66 and PCI outputs.
VDD3.3V
4, 10, 16, 22,
27, 29, 36, 38,
43, 49, 56
I
3.3-V power for core and the HCLK/HCLK, 3VMREF/3VMREF, 3V48, 3V66, and PCI outputs.
XIN
5
I
Crystal input – 14.318 MHz
XOUT
6
O
Crystal output – 14.318 MHz
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDC930DLG4 | 功能描述:鎖相環(huán) - PLL 133-MHz Clock Synth/ Drvr RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CDC930DLR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CDC950 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS/SERVERS |
| CDC950DGG | 功能描述:時鐘合成器/抖動清除器 133MHz Clk Synth RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CDC950DGGG4 | 功能描述:時鐘合成器/抖動清除器 133MHz Clk Synth RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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