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參數(shù)資料
| 型號： | CDC9163 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PC Motherboard Clock Sythesizer/Drivers with SDRAM Clock Support(PC時鐘合成器/驅(qū)動器(SDRAM 時鐘支持)) |
| 中文描述： | 電腦主板時鐘Sythesizer /支持與SDRAM時鐘驅(qū)動器（電腦時鐘合成器/驅(qū)動器（SDRAM的時鐘支持）） |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 177K |
| 代理商： | CDC9163 |
CDC9163
PC CLOCK SYNTHESIZER/DRIVER
WITH SDRAM CLOCK SUPPORT
SCAS574 – JULY 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
MAX
UNIT
Stabilization time
After change to SEL0, SEL1, or SEL2
3
ms
After power up
3
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at XIN.
switching characteristics (see Figures 1, and 2)
PARAMETER
FROM
(INPUT)
TO
MIN
MAX
UNIT
(OUTPUT)
Host clocks
Jitter
tr
tf
Duty cycle
tskew
HCLKn
±
250
ps
HCLKn
0.4
2
ns
HCLKn
0.4
2
ns
HCLKn
45
55
%
HCLKn
250
ps
Clock enable latency
HCLK EN
HCLK_EN
HCLKn
↑
1
4
HCLK
cycles
PCI clocks
Jitter
tr
tf
Duty cycle
tskew
thpoffset
PCKLn
±
350
ps
PCKLn
0.5
2.0
ns
PCKLn
0.5
2.0
ns
PCKLn
45
55
%
PCKLn
500
ps
HCLKn
PCKLn
1
4
ns
Clock enable latency
PCLK EN
PCLK_EN
PCLKn
↑
1
4
HCLK
cycles
Fixed clocks (REF, SBCLK, FCCLK)
REF1, SBCLK, FCCLK
1
4
ns
tr
REF0
0.5
2
REF1, SBCLK, FCCLK
1
4
ns
tf
REF0
0.5
2
Duty cycle
REF1, SBCLK, FCCLK
45
55
%
Specifications are applicable only after the PLL stabilization time has elapsed.
Rise and fall times are characterized using the load circuits shown in Figure 1.
P
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