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參數(shù)資料
| 型號(hào)： | CDC9163 |
| 廠(chǎng)商： | Texas Instruments, Inc. |
| 英文描述： | PC Motherboard Clock Sythesizer/Drivers with SDRAM Clock Support(PC時(shí)鐘合成器/驅(qū)動(dòng)器(SDRAM 時(shí)鐘支持)) |
| 中文描述： | 電腦主板時(shí)鐘Sythesizer /支持與SDRAM時(shí)鐘驅(qū)動(dòng)器（電腦時(shí)鐘合成器/驅(qū)動(dòng)器（SDRAM的時(shí)鐘支持）） |
| 文件頁(yè)數(shù)： | 2/9頁(yè) |
| 文件大?。?/td> | 177K |
| 代理商： | CDC9163 |
CDC9163
PC CLOCK SYNTHESIZER/DRIVER
WITH SDRAM CLOCK SUPPORT
SCAS574 – JULY 1996
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
HCLK(1:12)
47, 45, 42, 41,
39, 38, 37, 36,
34, 33, 9, 8
Output
3.3-V CPU SDRAM Clocks. Twelve HCLKs are programmable with SEL(0:2) as shown in
the Frequency-Select table. HCLKs are set low when HCLK_EN is low.
PCI(1:6)
11, 12, 13, 14,
16, 17
Output
3.3 V PCI Clocks. Six PCI clocks operate at 1/2 the HCLK frequency. PCI clocks are set
low when PCLK_EN is low.
SBCLK
23
Output
Serial bus clock. SBCLK provides 3.3-V universal serial bus 48-MHz clock output.
FCCLK
22
Output
Floppy controller clock. FCCLK provides 3.3-V floppy controller clock output at 24 MHz.
REF(1:2)
1, 2
Output
Reference clock. REF provides 3.3-V ISA reference clock output at 14.318 MHz
XIN
4
Input
Crystal (or oscillator) input
XOUT
5
Output
Crystal output
HCLK_EN
31
Input
Host clock enable. When HCLK_EN is low, HCLKs are set low. HCLK_EN has pulldown
resistor on the input.
PCI_EN
25
Input
PCI clock enable. When PCI_EN is low, PCIs are low. PCI_EN has a pulldown resistor on
the input.
OE
28
Input
Output enable. OE is the output-enable for all outputs except XOUT. When OE is high,
outputs are enabled. When OE is low, outputs are disabled to a high-impedence state.
SEL(0:2)
26, 27
Input
Host clock frequency select. SEL operation is shown in frequency-select table.
VCC
20, 21, 28, 48
Power
3.3-V core power supply
VCC(CPU)
VCC(PCI)
6, 32, 40, 46
Power
3.3-V host clock output power supply
15
Power
3.3-V PCI clock output power supply
GND
3, 10, 18, 19,
24, 30, 35, 43,
44
GND
Ground
FREQUENCY SELECT
OE
SEL2
SEL1
SEL0
XIN
HCLKn
PCIn
REFn
SBCLK
FCCLK
L
X
X
X
14.31818 MHz
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
H
L
L
L
14.31818 MHz
75 MHz
37.5 MHz
14.318 MHz
48 MHz
24 MHz
H
L
L
H
14.31818 MHz
TBD
TBD
14.318 MHz
48 MHz
24 MHz
H
L
H
L
14.31818 MHz
TBD
TBD
14.318 MHz
48 MHz
24 MHz
H
L
H
H
14.31818 MHz
83.3MHz
41.6 MHz
14.318 MHz
48 MHz
24 MHz
H
H
L
L
14.31818 MHz
50 MHz
25 MHz
14.318 MHz
48 MHz
24 MHz
H
H
L
H
14.31818 MHz
60 MHz
30 MHz
14.318 MHz
48 MHz
24 MHz
H
H
H
L
14.31818 MHz
66.6 MHz
33.3 MHz
14.318 MHz
48 MHz
24 MHz
H
H
H
H
14.31818 MHz
55 MHz
27.5
14.318 MHz
48 MHz
24 MHz
The allowable reference frequency is minimum = 14.316 MHz, nominal = 14.31818 MHz, and maximum = 14.32 MHz.
CLOCK ENABLE TABLE
HCLK_EN
PCI_EN
HCLKn
PCIn
L
L
Running
Running
L
H
Running
L
H
L
L
Running
H
H
L
L
P
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