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參數(shù)資料
| 型號： | CDC913DB |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS |
| 中文描述： | PC主板時鐘發(fā)生器，雙1至4緩沖器和三態(tài)輸出 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 156K |
| 代理商： | CDC913DB |
CDC913
PC MOTHERBOARD CLOCK GENERATOR
WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS
SCAS502C – APRIL 1995 – REVISED MAY 1996
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics (see Figures 1 and 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V,
TA = 25
°
C
MIN
VCC = 3.135 V to 3.6 V,
TA = 0
°
C to 70
°
C
MIN
UNIT
TYP
MAX
MAX
tPLH
1A
1Yn
1.5
3.5
1.2
3.8
ns
2A
2Yn
1.5
3.5
1.2
3.8
tPHL
1A
1Yn
1.5
3.5
1.2
3.8
ns
2A
2Yn
1.5
3.5
1.2
3.8
tPZH
OE
1Yn
2.5
7
2
7.5
ns
2Yn
2.5
7
2
7.5
tPZL
OE
1Yn
2.5
7
2
7.5
ns
2Yn
2.5
7
2
7.5
tPHZ
OE
1Yn
2.5
7
2
7.5
ns
2Yn
2.5
7
2
7.5
tPLZ
OE
1Yn
2.5
7
2
7.5
ns
2Yn
2.5
7
2
7.5
1Yn
350
350
tsk(o)
2Yn
350
350
ps
( )
Any Y
500
500
tsk(p)
1Yn and 2Yn
1
1
ns
CPUCLK
±
250
±
350
Jitter(pk pk)
ps
Jitter(pk-pk)
PCICLK
PCICLK
30
SEL0 = L,
SEL1 = L
20
tc(period)
CPUCLK
SEL0 = H,
SEL1 = L
16.7
ns
SEL0 = L,
SEL1 = H
15
D t c cle
Duty cycle
CPUCLK
45%
55%
PCICLK
45%
55%
tr
tf
2
ns
2
ns
Specifications are applicable only after the PLL stabilization time has elapsed.
Rise and fall times are characterized using the load circuits shown in Figure 1.
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參數(shù)描述 |
|---|---|
| CDC913DW | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| CDC9161DL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU System Clock Generator |
| CDC921 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIRECT RAMBUSE CLOCK GENERATOR |
| CDC921DL | 制造商:Texas Instruments 功能描述: |
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