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參數(shù)資料
| 型號： | CDC913DB |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS |
| 中文描述： | PC主板時鐘發(fā)生器，雙1至4緩沖器和三態(tài)輸出 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大小： | 156K |
| 代理商： | CDC913DB |
CDC913
PC MOTHERBOARD CLOCK GENERATOR
WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS
SCAS502C – APRIL 1995 – REVISED MAY 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25
°
C
TYP
MIN
TYP
MAX
UNIT
MIN
MAX
VIK
VCC = 3.135 V,
II = –18 mA
IOH = –12 mA
IOH = –6 mA
IOH = –6 mA
IOH = –12 mA
IOH= 12 mA
IOH = –12 mA
IOL = 12 mA
IOL = 6 mA
IOL = 6 mA
IOL = 12 mA
IOL= 12 mA
IOL = 12 mA
VI = VCC or GND
VO = 3 V or 0
–1.2
–1.2
V
REFCLK
2.5
2.4
PCICLK
2.5
2.4
VOH
VCC = 3.135 V
CPUCLK
2.5
2.4
V
1Yn
2.5
2.4
2Yn
2 5
2.5
2 4
2.4
REFCLK
0.4
0.5
PCICLK
0.4
0.5
VOL
VCC = 3.135 V
CPUCLK
0.4
0.5
V
1Yn
0.4
0.5
2Yn
0 4
0.4
0 5
0.5
II
IOZ
VCC = 3.6 V,
VCC = 3.6 V,
±
1
±
1
±
1
±
1
1
μ
A
μ
A
VCC = 3.6 V,
VI= VCCor GND
VI = VCC or GND
3 6 V
IO = 0,
Outputs high
ICC
Outputs low
1
mA
Outputs disabled
1
Ci
Co
VI = 3.135 V or 0
VI = 3.135 V or 0
6
pF
6
pF
All typical values are at VCC = 3.3 V, TA = 25 C.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
MAX
UNIT
Stabilization time
After SEL1, SEL0
After power up
5
5
ms
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at X1. Until phase lock is obtained, the specifications for propagation delay and
skew parameters given in the switching characteristics table are not applicable.
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