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參數(shù)資料
| 型號(hào)： | CDC2510APWRG4 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 3.3-V PHASE-LOCK LOOP CLOCK DRIVER |
| 中文描述： | 3.3 - V相位鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 311K |
| 代理商： | CDC2510APWRG4 |
SCAS604C APRIL 1998 REVISED DECEMBER 2004
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Use
CDCVF2510A
as a Replacement for
this Device
Spread Spectrum Clock Compatible
100-MHz Maximum Frequency
Available in Plastic 24-Pin TSSOP
Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
Distributes One Clock Input to One Bank of
Ten Outputs
Single Output Enable Terminal Controls All
Ten Outputs
External Feedback (FBIN) Pin Is Used to
Synchronize the Outputs to the Clock Input
On-Chip Series Damping Resistors
No External RC Network Required
Operates at 3.3-V V
CC
description
The CDC2510A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
It is specifically designed for use with synchronous DRAMs. The CDC2510A operates at 3.3-V V
CC
and provides
integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted
to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output
enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input
is low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDC2510A does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2510A requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback
signals. The PLL can be bypassed for test purposes by strapping AV
CC
to ground.
The CDC2510A is characterized for operation from 0
°
C to 70
°
C.
FUNCTION TABLE
INPUTS
OUTPUTS
G
CLK
1Y
(0:9)
FBOUT
X
L
L
L
L
H
L
H
H
H
H
H
Copyright
2004, Texas Instruments Incorporated
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
CLK
AV
CC
V
CC
1Y9
1Y8
GND
GND
1Y7
1Y6
1Y5
V
CC
FBIN
1
2
3
4
5
6
7
8
9
10
11
12
AGND
V
CC
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
V
CC
G
FBOUT
24
23
22
21
20
19
18
17
16
15
14
13
PW PACKAGE
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| CDC2510BPWR | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 3.3VPhase Lock Loop ClockDrvr RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDC2510BPWRG4 | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 3.3V Ph-Lock Loop Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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