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參數(shù)資料
| 型號(hào)： | CDB4955A |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 17/60頁 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD FOR CS4955A |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 視頻，視頻處理 |
| 嵌入式： | 是，其它 |
| 已用 IC / 零件： | CS4955 |
| 主要屬性： | NTSC/PAL 數(shù)字視頻編碼器 |
| 次要屬性： | 圖形用戶界面，RS-232 接口 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | CS4954-CQZR-ND - IC VID ENCODER NTSC/PAL 48-TQFP 598-1682-ND - IC VIDEO ENCODER NTSC/PAL 48TQFP |
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CS4954 CS4955
24
DS278F6
all 4 bytes to be inserted to the registers and then
enables closed caption insertion and interrupts. As
the closed caption interrupts occur, the host soft-
ware responds by writing the next two bytes to be
inserted to the correct control registers and then
clears the interrupt and waits for the next field.
5.9
Programmable H-sync and V-sync
It is possible in master mode to change the H-sync
and V-sync times based on register settings. Pro-
grammable H-sync and V-sync timing is helpful in
systems where control signal latencies are present.
The user can then program H-sync and V-sync tim-
ing according to their system requirements. The de-
fault values are 244, and 264 for NTSC and PAL
respectively.
H-sync can be delayed by a full line, in 74 nsec in-
tervals.
V-sync can be shifted in time in both directions.
The default values are 18 and 23 for NTSC and
PAL respectively. Since the V-sync register is 5
bits wide (Sync Register 0), the V-sync pulse can
be shifted by 31 lines total.
V-sync timing can preceed its default timing by a
maximum of 18 lines (NTSC) or 23 lines (PAL)
and can be delayed from its default timing by a
maximum of 13 lines (NTSC) or 8 lines (PAL).
5.10 Wide Screen Signaling (WSS) and
CGMS
Wide screen signaling support is provided for
NTSC and for PAL standards. Wide screen signal-
ing is currently used in most countries with 625 line
systems as well as in Japan for EDTV-II applica-
tions. For a complete description of the WSS stan-
dard, please refer to ITU-R BT.1119 (625 line
system) and to EIAJ CPX1204 for the Japanese
525 line system standard.
The wide screen signal is transferred in a blanking
line of each video field (NTSC: lines 20 and 283,
PAL: lines 23 and 336). Wide screen signaling is
enabled by setting WW_23 to “1”. Some countries
with PAL standard don’t use line 336 for wide
screen signaling (they use only line 23), therefore
we provide another enable bit (WSS_22) for that
particular line.
There are 3 registers dedicated to contain the trans-
mitted WSS bits (WSS_REG_0, WSS_REG_1,
WSS_REG_2). The data insertion into the appro-
priate lines is performed automatically by this de-
vice. The run-in and start code bits do not have to
be loaded into this device. It automatically inserts
the correct code at the beginning of transfer.
5.11 Teletext Support
This chip supports several teletext standards in-
cluding European teletext, NABTS (North Ameri-
can teletext), and WST (World Standard Teletext)
for NTSC and PAL.
All of these teletext standards are defined in the
ITU-R BT.653-2 document. The European tele-
text is defined as “teletext system B” for
625/50 Hz TV systems. NABTS teletext is defined
as “teletext system C” for 525/60 Hz TV systems.
WST for PAL is defined as “teletext system D”
for 624/50 Hz TV systems and WST for NTSC is
defined as “teletext system D” for 525/60 Hz TV
systems.
This chip provides independant teletext encoding
into composite 1, composite 2 and s-video signals.
The teletext encoding into these various signals is
software programmable.
In teletext pulsation mode, (TTX_WINDOW=0),
register 0×31 bit 3, the pin TTXDAT receives a
teletext bitstream sampled at the 27 MHz clock. At
each rising edge of the TTXRQ output signal a sin-
gle teletext bit has to be provided after a program-
mable input delay at the TTXDAT input pin.
Phase variant interpolation of the data in the inter-
nal teletext encoder results in minimal phase jitter
on the ouput text lines.
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