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參數(shù)資料
| 型號： | CDB4955A |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 11/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVALUATION BOARD FOR CS4955A |
| 標準包裝： | 1 |
| 主要目的： | 視頻，視頻處理 |
| 嵌入式： | 是，其它 |
| 已用 IC / 零件： | CS4955 |
| 主要屬性： | NTSC/PAL 數(shù)字視頻編碼器 |
| 次要屬性： | 圖形用戶界面，RS-232 接口 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | CS4954-CQZR-ND - IC VID ENCODER NTSC/PAL 48-TQFP 598-1682-ND - IC VIDEO ENCODER NTSC/PAL 48TQFP |
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CS4954 CS4955
DS278F6
19
Field two begins with VSYNC transitioning low at
line 266. VSYNC stays low for 3 line cycles and
transitions high during the end of line 268. Video
input on the V [7:0] pins is expected between line
284 and line 522. Field two is 263 lines; field one
is 262 lines.
5.2.9 PAL Progressive Scan
VSYNC will transition low at the beginning of the
odd field and will remain low for 2.5 lines or 2160
pixel cycles (864 × 2.5). PAL non-interlaced tim-
ing is illustrated in Figure 10. In this mode, the
CS4954/5 expects digital video input on the V [7:0]
pins for 288 lines, beginning on active video line 23
and continuing through line 309.
The second field begins with VSYNC transitioning
low after 312 lines from the beginning of the first
field. VSYNC stays low for 2.5 line-times and tran-
sitions high during the middle of line 315. Video
input on the V [7:0] pins is expected between line
335 through line 622. Field two is 313 lines; field
one is 312 lines.
5.3
ITU-R.BT656
The CS4954/5 supports an ITU-R.BT656 slave
mode feature that is selectable through the ITU-
R.BT656 bit of the CONTROL_0 Register. The
ITU-R.BT656 slave feature is unique because the
horizontal and vertical timing and digital video are
combined into a single 8-bit 27 MHz input. With
ITU-R.BT656 there are no horizontal and vertical
input or output strobes, only 8-bit 27 MHz active
CbYCrY data, with start- and end-of-video codes
implemented using reserved 00 and FF code se-
quences within the video feed. As with all modes,
V [7:0] are sampled with the rising edge of CLK.
The CS4954/5 expects the digital ITU-R.BT656
stream to be error-free. The FIELD(1) output tog-
gles as with non ITU-R.BT656 input. ITU-
R.BT656 input timing is illustrated in Figure 11.
523
524
525
1
2
3
4
5
6
7
8
9
VSYNC Drops
10
22
Analog
Field 1
261
262
263
Analog
Field 2
285
284
272
271
270
269
268
267
266
265
264
523
524
525
12
3
4
5
6
7
8
9
VSYNC Drops
10
22
Analog
Field 3
261
262
263
Analog
Field 4
285
284
272
271
270
269
268
267
266
265
264
Burst begins with positive half-cycle
Burst begins with negative half-cycle
Figure 7. NTSC Video Interlaced Timing
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDB-496122-EV2 | 制造商:Cirrus Logic 功能描述: |
| CDB496122-EV2 | 功能描述:音頻 IC 開發(fā)工具 Eval Bd CobraNet Trnspt/AdNtwrk Prcsr RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| CDB49X | 制造商:Cirrus Logic 功能描述:EVAL BD - BASE BOARD FOR AUDIO DSP - Boxed Product (Development Kits) |
| CDB-5 | 功能描述:電線導管 5’ Brown RoHS:否 制造商:Panduit 類型:Slotted SideWall Open finger design wiring cut 材料:Polypropylene 顏色:Light Gray 大小: 最大光束直徑: 抗拉強度: 外部導管寬度:25 mm 外部導管高度:25 mm |
| CDB5012 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Evaluation Board |
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