參數(shù)資料
型號: CDB4384
廠商: Cirrus Logic Inc
文件頁數(shù): 15/52頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR CS4384 DAC
標(biāo)準(zhǔn)包裝: 1
DAC 的數(shù)量: 8
位數(shù): 24
采樣率(每秒): 192k
數(shù)據(jù)接口: 串行
DAC 型: 電壓
工作溫度: -40°C ~ 85°C
已供物品:
已用 IC / 零件: CS4384
產(chǎn)品目錄頁面: 757 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: CS4384-CQZR-ND - IC DAC 8CH 103DB 192KHZ 48-LQFP
598-1062-ND - IC DAC 8CH 103DB 192KHZ 48LQFP
其它名稱: 598-1525
22
DS620F1
CS4384
4.3
Digital Interface Formats
The serial port operates as a slave and supports the IS, Left-Justified, Right-Justified, One-Line Mode
(OLM) and TDM digital interface formats with varying bit depths from 16 to 32 as shown in Figures 9-19.
Data is clocked into the DAC on the rising edge. OLM and TDM configurations are only supported in Soft-
ware Mode.
LRCK
SCLK
Left Channel
Right Channel
SDINx
+3 +2 +1
+5 +4
-1 -2 -3 -4 -5
+3 +2 +1
+5 +4
-1 -2 -3 -4
MSB
LSB
MSB
LSB
Figure 9. Format 0 - Left-Justified up to 24-bit Data
LRCK
SCLK
Left Channel
Right Channel
SDINx
+3 +2 +1
+5 +4
-1 -2 -3 -4 -5
+3 +2 +1
+5 +4
-1 -2 -3 -4
MSB
LSB
Figure 10. Format 1 - IS up to 24-bit Data
LRCK
SCLK
Left Channel
Right Channel
SDINx
65
432
1
0
98
7
15 14 13 12 11 10
6
543
2
1
0
98
7
15 14 13 12 11 10
32 clocks
Figure 11. Format 2 - Right-Justified 16-bit Data
LRCK
SCLK
Left Channel
SDINx
65
432
1
0
7
23 22 21 20 19 18
6
543
2
1
0
7
23 22 21 20 19 18
32 clocks
0
Right Channel
Figure 12. Format 3 - Right-Justified 24-bit Data
LRCK
SCLK
Left Channel
Right Channel
SDINx
654
3210
987
15 14 13 12 11 10
10
654321
0
987
15 14 13 12 11 10
17 16
32 clocks
19 18
Figure 13. Format 4 - Right-Justified 20-bit Data
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