參數(shù)資料
型號： CD4027BMS
廠商： Intersil Corporation
英文描述： CMOS Dual J-K Master-Slave Flip-Flop(CMOS雙 J-K主從觸發(fā)器)
中文描述： CMOS雙JK主從觸發(fā)器（的CMOS雙JK主從觸發(fā)器）
文件頁數(shù)： 4/8頁
文件大?。?/td> 72K
代理商： CD4027BMS
7-783
Specifications CD4027BMS
Output Current (Source)
IOH15
VDD =15V, VOUT = 13.5V
1, 2
+125
o
C
-55
o
C
-
-2.4
mA
-
-4.2
mA
Input Voltage Low
VIL
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
-
3
V
Input Voltage High
VIH
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
7
-
V
Propagation Delay
Clock To Q, Q
TPHL1
TPLH1
VDD = 10V
1, 2, 3
-
130
ns
VDD = 15V
1, 2, 3
-
90
ns
Propagation Delay
Set To Q, Reset To Q
TPLH2
VDD = 10V
1, 2, 3
-
130
ns
VDD = 15V
1, 2, 3
-
90
ns
Propagation Delay
Set To Q, Reset To Q
TPHL3
VDD = 10V
1, 2, 3
-
170
ns
VDD = 15V
1, 2, 3
-
120
ns
Transition Time
TTHL
TTLH
VDD = 10V
1, 2, 3
-
100
ns
VDD = 15V
1, 2, 3
-
80
ns
Maximum Clock Input
Frequency Toggle Mode
Input TR, TF = 5ns
FCL
VDD = 10V
1, 2, 3
8
-
MHz
VDD = 15V
1, 2, 3
12
-
MHz
Minimum Data Setup
Time
TS
VDD = 5V
1, 2, 3
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
-
200
ns
VDD = 10V
1, 2, 3
-
75
ns
VDD = 15V
1, 2, 3
-
50
ns
Minimum Set or Reset
Pulse Width
TW
VDD = 5V
1, 2, 3
-
180
ns
VDD = 10V
1, 2, 3
-
80
ns
VDD = 15V
1, 2, 3
-
50
ns
Minimum Clock Pulse
Width
TW
VDD = 5V
1, 2, 3
-
140
ns
VDD = 10V
1, 2, 3
-
60
ns
VDD = 15V
1, 2, 3
-
40
ns
Clock Input Rise Or Fall
Time (Note 5)
TRCL
TFCL
VDD = 5V
1, 2, 3, 4
-
45
μ
s
VDD = 10V
1, 2, 3, 4
-
5
μ
s
VDD = 15V
1, 2, 3, 4
-
2
μ
s
Input Capacitance
CIN
1, 2
-
7.5
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. If more than one unit is cascaded in a parallel clocked operation, trCL should be made less than or equal to the sum of the fixed propa-
gation delay time at 15pF and the transition time of the output driving stage for the estimated capacitive load.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
+25
o
C
LIMITS
UNITS
MIN
MAX
Supply Current
IDD
VDD = 20V, VIN = VDD or GND
1, 4
-
7.5
μ
A
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
(Continued)
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX
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CD4027BNS 制造商:Texas Instruments 功能描述:
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