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參數(shù)資料
| 型號： | CD40100BMS |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS 32-Stage Static Left/Right Shift Register |
| 中文描述： | 的CMOS 32級靜態(tài)左/右移位寄存器 |
| 文件頁數(shù)： | 9/9頁 |
| 文件大小： | 65K |
| 代理商： | CD40100BMS |
7-1285
CD40100BMS
FIGURE 8. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF CLOCK FREQUENCY
Timing Diagram
FIGURE 9. TIMING DIAGRAM DEFINING SETUP, HOLD, AND PROPAGATION DELAY TIMES
Chip Dimensions and Pad Layout
Typical Performance Characteristics
(Continued)
8
6
4
2
CLOCK INPUT FREQUENCY (fCL) (KHz)
1
6
4
2
10
3
P
μ
W
SUPPLY VOLTAGE (VDD) = 15V
10V
10V
5V
10
4
10
5
10
2
A
A
)
o
C
L
8
6
4
2
8
6
4
2
8
6
4
2
8
8
10
2
6
4
2
10
8
10
3
6
4
2
8
6
4
2
8
6
4
2
10
4
I
(
CL = 50pF
CL =15pF
CLOCK
INPUT
OUTPUT
tWH
tWL
tS
tH
tPHL
tPHL
Dimensions in parenthesis are in millimeters and are derived from
the basic inch dimensions as indicated. Grid graduations are in mils
(10
inch).
METALLIZATION:
PASSIVATION:
BOND PADS:
DIE THICKNESS:
Thickness: 11k
14k
, AL.
10.4k - 15.6k
, Silane
0.004 inches X 0.004 inches MIN
0.0198 inches - 0.0218 inches
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