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參數(shù)資料
| 型號(hào)： | CD40100BMS |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS 32-Stage Static Left/Right Shift Register |
| 中文描述： | 的CMOS 32級(jí)靜態(tài)左/右移位寄存器 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 65K |
| 代理商： | CD40100BMS |
1282
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
Specifications CD40100BMS
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K
±
5%, VDD = 18V
±
0.5V
2. Each pin except VDD and GND will have a series resistor of 47K
±
5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V
±
0.5V
TABLE 9. DATA TRANSFER TABLE*
INITIAL STATE
CLOCK
RESULTING STATE
DATA INPUT
CLOCK INHIBIT
INTERNAL STAGE
LEVEL CHANGE
INTERNAL
STAGE Q
OUTPUT
0
0
X
0
NC
X
0
0
NC
0
1
0
X
1
NC
X
0
1
NC
1
X
1
1
X
NC
NC
0 = Low Level
1 = High Level
X = Don’t Care
NC = No Change
* For Shift-Right Mode
Data Input = SHIFT RIGHT INPUT (Term. 11)
Internal Stage = Stage 1 (Q1)
Output = SHIFT LEFT OUTPUT (Term. 4)
For Shift Left Mode
Data Input = SHIFT LEFT INPUT (Term. 6)
Internal Stage = Stage 32 (Q32)
Output = SHIFT RIGHT OUTPUT (Term. 12)
TABLE 10. CONTROL TRUTH TABLE
LEFT/RIGHT
CONTROL
CLOCK INHIBIT
RECIRCULATE
CONTROL
ACTION
INPUT BIT ORIGIN
1
0
1
Shift Left
Shift Left Input
1
0
0
Shift Left
Stage 1
0
0
1
Shift Right
Shift Right Input
0
0
0
Shift Right
Stage 32
X
1
X
No Shift
-
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
(Continued)
FUNCTION
OPEN
GROUND
VDD
9V
±
-0.5V
OSCILLATOR
50kHz
25kHz
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