
SmartRF
CC2420
Pin
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Pin Name
AVDD_RF2
AVDD_IF2
NC
AVDD_ADC
DVDD_ADC
DGND_GUARD
DGUARD
RESETn
DGND
DSUB_PADS
DSUB_CORE
DVDD3.3
DVDD1.8
SFD
CCA
FIFOP
Pin type
Power (analog)
Power (analog)
-
Power (analog)
Power (digital)
Ground (digital)
Power (digital)
Digital Input
Ground (digital)
Ground (digital)
Ground (digital)
Power (digital)
Power (digital)
Digital output
Digital output
Digital output
Pin Description
1.8 V Power supply for receive and transmit mixers
1.8 V Power supply for transmit / receive IF chain
Not Connect
1.8 V Power supply for analog parts of ADCs and DACs
1.8 V Power supply for digital parts of receive ADCs
Ground connection for digital noise isolation
1.8 V Power supply connection for digital noise isolation
Asynchronous, active low digital reset
Ground connection for digital core and pads
Substrate connection for digital pads
Substrate connection for digital modules
3.3 V Power supply for digital I/Os
1.8 V Power supply for digital core
SFD (Start of Frame Delimiter) / digital mux output
CCA (Clear Channel Assessment) / digital mux output
High when number of bytes in FIFO exceeds threshold /
serial RF clock output in test mode
High when data in FIFO /
serial RF data input / output in test mode
SPI Chip select, active low
SPI Clock input, up to 10 MHz
SPI Slave Input. Sampled on the positive edge of SCLK
SPI Slave Output. Updated on the negative edge of SCLK.
Tristate when CSn high.
1.8 V Power supply for digital RAM
Not Connect
1.8 V crystal oscillator power supply
16 MHz Crystal oscillator pin 2
16 MHz Crystal oscillator pin 1 or external clock input
Not Connect
Voltage regulator enable, active high, held at
VREG_IN
voltage level when active
Voltage regulator 1.8 V power supply output
Voltage regulator 2.1 to 3.6 V power supply input
1.8 V Power supply for transmit / receive IF chain
External precision resistor, 43 k
,
±
1 %
Analog test I/O for prototype and production testing
Analog test I/O for prototype and production testing
1.8 V Power supply for phase detector and charge pump
30
FIFO
Digital I/O
31
32
33
34
CSn
SCLK
SI
SO
Digital input
Digital input
Digital input
Digital output
(tristate)
Power (digital)
-
Power (analog)
Analog I/O
Analog I/O
-
Digital input
35
36
37
38
39
40
41
DVDD_RAM
NC
AVDD_XOSC16
XOSC16_Q2
XOSC16_Q1
NC
VREG_EN
42
43
44
45
46
47
48
VREG_OUT
VREG_IN
AVDD_IF1
R_BIAS
ATEST2
ATEST1
AVDD_CHP
Power output
Power (analog)
Power (analog)
Analog output
Analog I/O
Analog I/O
Power (analog)
NOTES:
The exposed die attach pad
must
be connected to a solid ground plane as this is the main ground connection for the
chip.
Note that digital inputs
SCLK
,
SI
and
CSn
are high-impedance inputs (no internal pull-up) and should have external
pull-ups if not driven.
SO
is high-impedance when
CSn
is high. An external pull-up should be used at
SO
to prevent
floating input at microcontroller.
Chipcon AS
SmartRF
CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09
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