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參數(shù)資料
| 型號(hào)： | CB45000 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | HCMOS6 STANDARD CELLS |
| 中文描述： | HCMOS6標(biāo)準(zhǔn)單元 |
| 文件頁(yè)數(shù)： | 3/16頁(yè) |
| 文件大?。?/td> | 265K |
| 代理商： | CB45000 |
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CB45000 SERIES
TECHNOLOGY OVERVIEW
A major feature of the HCMOS6 process is
salicided active areas. This results in source
drain areas that are on the order of one to two
ohms resistance as opposed to the hundreds or
thousands of ohms of source drain resistance in
non-salicided
technologies.
resistance is one reason that very low transistor
widths could be utilized in the cell design since
drive is not lost due to source drain resistance.
This
very
low
This use of low width transistors results in lower
capacitance loading of the gates due to the
smaller areas utilized. Low resistance, low
capacitance, and small gates results in low power
usage for inverters as compared to previous
technologies.
The
consumption allows the usage of salicided active
stripes to distribute power internally to the simple
cell, replacing, in some cases, the usage of the
first metal layer. This saves silicon area by
allowing greater density, permeability and
routability of the cells resulting in greater overall
circuit density.
reduction
in
power
The other major feature of the HCMOS6 process
is five metal layer interconnect using CMP
(Chemical Mechanical Polishing) planarization.
The use of CMP for improved planarity between
metal layers allows the use of additional
interconnect layers without yield degradation,
improving density whilst retaining low costs.
The power distribution methodology provides
separate internal distributions to improve product
noise margin and reduce power loss. The three
supplies are:
Internal Vdd and Vss
Serves the core cells and the prebuffer sec-
tions of the I/O
External Vdd and Vss
Serves the output transistors only
Receiver Vdd and Vss
Serves the first stages of the receiver cells.
Optional distributions for 5.0V interface and other
standards can be utilized as necessary.
I
I
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