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參數(shù)資料
| 型號(hào)： | CB45000 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | HCMOS6 STANDARD CELLS |
| 中文描述： | HCMOS6標(biāo)準(zhǔn)單元 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 265K |
| 代理商： | CB45000 |
CB45000 SERIES
2/16
GENERAL DESCRIPTION
The CB45000 standard cell series uses a high
performance, low voltage, 5 level metal,
HCMOS6 0.35 micron process to achieve sub-
nanosecond internal speeds while offering very
low power dissipation and high noise immunity.
With an average routed logic density of 14000
gates/mm
2
, the CB45000 family allows the
design of highly complex devices. The potential
available gate count ranges above 3 Million
equivalent gates. Devices can operate over a Vdd
voltage range of 2.7 to 3.6 volts.
The I/O count for this array family ranges to over
750 signals and 1000 pins based upon the
package technology utilized. A flexible I/O
approach has been developed to provide an
Figure 1
Process Overview
Metal 5 : Al-Cu
Metal 4 : Al-Cu
Metal 3 : Al-Cu
Metal 2 : Al-Cu
Metal 1 : W
optimum solution for today’s complex system
problems of drive levels and specialized interface
standards.
The product offers a variable bonding approach
supporting pad spacings from 80
μ
upwards and
supports staggered pad rows to address today’s
bonding technologies. Additional flexibility to
support 65
μ
and 50
μ
pad spacing will be
available in the near future.
The I/O can be configured for circuits ranging
from low voltage CMOS and TTL to low swing
differential circuits (LVDS) and the 1Gigabit per
second high speed link. Standards like SCSI, 3.3
and 5 Volt PCI and other 5.0 Volt interfaces are
currently being addressed.
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