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參數(shù)資料
| 型號： | C9835CTT |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Low-EMI Clock Generator for Intel Mobile 133-MHz/3 SO-DIMM Chipset Systems |
| 中文描述： | 低電磁干擾時(shí)鐘發(fā)生器英特爾移動(dòng)133兆赫/ 3的SO - DIMM芯片系統(tǒng) |
| 文件頁數(shù)： | 8/18頁 |
| 文件大?。?/td> | 343K |
| 代理商： | C9835CTT |
C9835
Document #: 38-07303 Rev. **
Page 8 of 18
Serial Control Registers
Following the acknowledge of the Address Byte, two additional
bytes must be sent:
1)
“
Command Code
“
byte
2)
“
Byte Count
”
byte.
Byte 0: CPU Clock Register (1 = Enable, 0 = Disable)
@Pup
[
15
]
Pin#
[
16
]
7
1
36
6
1
49
5
1
50
4
1
52
3
0
–
2
1
26
1
1
25
0
0
–
Byte 1: SDRAM Clock Register (1 = Enable, 0 = Disable)
@Pup
[
15
]
Pin#
[
16
]
7
0
–
6
0
–
5
1
39
4
1
40
3
1
42
2
1
43
1
1
45
0
1
46
Byte 2: 3C66 Clock Register (1 = Enable, 0 = Disable)
@Pup
[
15
]
Pin#
[
16
]
7
1
9
6
1
8
5
1
7
4
0
–
3
0
–
2
0
–
1
0
–
0
0
–
Byte 3: PCI Register (1 = Enable, 0 = Disable)
@Pup
[
17
]
Pin#
[
18
]
7
0
–
6
1
20
5
1
19
4
1
18
3
1
16
2
1
15
1
1
13
0
0
–
Notes:
15. The @Pup column gives the default state at power-up.
16. The Pin# column lists the relevant pin number where applicable.
Although the data (bits) in these two bytes are considered
“
don
’
t care,
”
they must be sent and will be acknowledged. After
the Command Code and the Byte Count have been acknowl-
edged, the sequence (Byte 0, Byte 1, and Byte 2) described
below will be valid and acknowledged.
Bit
Description
VCH_CLK
CPU2
CPU1
CPU0
Spread Spectrum ( 1 = enabled)
48M1(DOT)
48M0(USB)
Reserved. Set to 0
Bit
Description
Reserved. Set to 0
Reserved. Set to 0
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Bit
Description
3V66_2 (AGP)
3V66_1
3V66_0
Reserved. Set to 0
Reserved. Set to 0
Reserved. Set to 0
Reserved. Set to 0
Reserved. Set to 0
Bit
Description
Reserved. Set to 0
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1
SDRAM 133- MHz Mode Enable. Default is disabled =
“
0,
”
enabled =
“
1
”
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