參數(shù)資料
型號(hào): C9835CTT
廠商: Cypress Semiconductor Corp.
英文描述: Low-EMI Clock Generator for Intel Mobile 133-MHz/3 SO-DIMM Chipset Systems
中文描述: 低電磁干擾時(shí)鐘發(fā)生器英特爾移動(dòng)133兆赫/ 3的SO - DIMM芯片系統(tǒng)
文件頁(yè)數(shù): 11/18頁(yè)
文件大小: 343K
代理商: C9835CTT
C9835
Document #: 38-07303 Rev. **
Page 11 of 18
Maximum Ratings
Maximum Input Voltage Relative to V
SS
:............ V
SS
0.3V
Maximum Input Voltage Relative to V
DD
:.............V
DD
+ 0.3V
Storage Temperature: ................................
65
°
C to + 150
°
C
Operating Temperature:....................................0
°
C to +85
°
C
Maximum ESD Protection.............................................. 2 KV
Maximum Power Supply: ................................................5.5V
This device contains circuitry that protects the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V
IN
and V
OUT
should be constrained to
the range:
V
SS
< (V
IN
or V
OUT
) < V
DD
.
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DD
).
Notes:
20. All outputs loaded per
Table 7
.
21. Applicable to input signals : SEL(0:1), PD# (pull-up).
22. Applicable to SDATA and SCLK.
23. Internal pull-up and pull-down resistors affect this current.
24. See Applications data that is presented later in this datasheet on crystal interfacing.
DC Parameters
V
DD
= V
DDS
= 3.3V ± 5%, V
DDC
= V
DDI
= 2.5V ± 5%, T
A
= 0
°
C to +70
°
C
[20]
Parameter
Description
VIL1
Input Low Voltage
VIH1
Input High Voltage
VIL2
Input Low Voltage
VIH2
Input High Voltage
IIL1
Input Low Current (@V
IL
= V
SS
)
IIH1
Input High Current (@V
IH
=V
DD
)
Ioz
Three-state leakage Current
Idd3.3V
Dynamic Supply Current
Idd2.5V
Dynamic Supply Current
Conditions
Note 21
Min.
Typ.
Max.
1.0
Units
V
V
V
V
μA
μA
μA
mA
mA
mA
mA
mA
mA
pF
pF
nH
pF
V
μ
s
2.0
Note 22
1.0
2.2
For internal pull-up resistors
[23]
20
20
10
295
60
75
90
1
1
5
6
7
38
0.7V
DD
40
CPU @ 66 MHz
CPU @ 100 MHz
CPU @ 133 MHz
PD# =
0
PD# =
0
Ipd3.3V
Ipd2.5V
Cin
Cout
Lpin
Cxtal
V
BIAS
Txs
Power Down Supply Current
Power Down Supply Current
Input pin capacitance
Output pin capacitance
Pin inductance
Crystal pin capacitance
Crystal DC Bias Voltage
Crystal Startup time
Measured from Pin to Ground
[24]
34
36
0.3V
DD
V
DD
/2
From stable 3.3V power supply.
Table 7. Maximum Output Load
Clock Name
Max Load (in pF)
20
30
15
CPU(0:2), IOAPIC(0:1), REF, 48M0 (USB), VCH_CLK
PCI(0:6), SDRAM(0:5), DCLK, 3V66(0:2)
48M1 (DOT)
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