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參數(shù)資料
| 型號： | C9835CTT |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Low-EMI Clock Generator for Intel Mobile 133-MHz/3 SO-DIMM Chipset Systems |
| 中文描述： | 低電磁干擾時鐘發(fā)生器英特爾移動133兆赫/ 3的SO - DIMM芯片系統(tǒng) |
| 文件頁數(shù)： | 2/18頁 |
| 文件大?。?/td> | 343K |
| 代理商： | C9835CTT |
C9835
Document #: 38-07303 Rev. **
Page 2 of 18
Note:
3.
A bypass capacitor (0.1
μ
F) should be placed as close as possible to each positive power pin. If these bypass capacitors are not close to the pins their
high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
Pin Description
[
3
]
Pin
Name
PWR
VDD
VDD
Description
1
3
REF
XIN
3.3V 14.318 MHz clock output
Oscillator buffer input
. Connect to a crystal or to an external clock.
Oscillator buffer output
. Connect to a crystal. Do not connect when an external
clock is applied at X
IN
.
VDDC 2.5V Host bus clock outputs
VDD
3.3V Fixed 66.6 MHz clock outputs
3.3V PCI clock output
. This clock continues to run when PCI_STP# is at a logic
low level.
3.3V PCI clock outputs
. These clocks synchronously stop in a low state when
PCI_STP# is brought to a logic low level. They synchronously resume running
when PCI_STP# is brought to a logic high state.
VDD
3.3V Fixed 48 MHz clock outputs
3.3V selectable 66.6 MHz or 48 MHz clock output to VCH
. Spread spectrum
applies only when 66.6 MHz is selected. Select via SMBUS, byte 4 bit7.
CPU0 stop clock control input
. Stops only CPU0 in a low state when asserted
low. Using this pin to start and stop CPU0 clock insures synchronous (no short or
long clocks) transitioning of this clock.
PCI stop clock control input
. When this signal is at a logic low level (0), all PCI
clocks (except PCI_F) stop at a logic low level. Using this pin to start and stop PCI
clocks insures synchronous (no short or long clocks) transitioning of these clocks.
This pin has no effect on the PCI_F clock.
3.3V LVTTL inputs for logic selection
. These pins have Internal pull-ups,
typically 250k (range 200k to 800k).
Serial data input pin
. Conforms to the SMBUS specification of a Slave
Receive/Transmit device. This pin is an input when receiving data. It is an open
drain output when acknowledging or transmitting data. See 2-Wire SMBUS
Control Interface on page 7.
Serial clock input pin
. Conforms to the SMBUS specification. See 2-Wire
SMBUS Control Interface on page 7.
3.3V LVTTL-compatible input
. When held LOW, the device enters a power down
mode. This pin has an Internal Pull-Up. See Power Management Functions on
page 3.
VDD
3.3V LVTTL compatible input for selecting test mode
. See
Table 1
.
3.3V SDRAM feedback clock output
. See
Table 1
for frequency selection. See
Figure 4
for timing relationship.
4
XOUT
VDD
49, 50, 52
7, 8, 9
CPU(0:2)
3V66(0:2)
12
PCI_F
VDDP
13, 15, 16, 18,
19, 20
PCI (1:6)
VDDP
25, 26
48M(0,1)
36
VCH_CLK
VDD
34
CPU_STP#
VDD
11
PCI_STP#
VDD
28, 29
SEL(0,1)
VDD
30
SDATA
VDD
31
SCLK
VDD
32
PD#
VDD
33
TEST#
38
DCLK
VDDS
39, 40, 42, 43,
45, 46
54, 55
37, 44
17
53
51
2, 10, 27, 35
22
23
5, 6, 14, 21, 24,
41, 47, 48, 56
SDRAM(0:5)
VDDS 3.3V SDRAM clock outputs
IOAPIC(0,1)
VDDS
VDDP
VDDI
VDDC
VDD
AVDD
AVSS
VDDI
2.5V IOAPIC clock outputs. See
Figure 4
for timing relationships.
3.3V Power for SDRAM and DCLK clock output buffers
3.3V Power for PCI clock output buffers
2.5V Power for IOAPIC clock output buffers
2.5V Power for CPU clock output buffers
3.3V Common power supply
Analog power
Analog ground
VSS
Common ground pins
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相關(guān)代理商/技術(shù)參數(shù) |
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| C9835CY | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Low-EMI Clock Generator for Intel Mobile 133-MHz/3 SO-DIMM Chipset Systems |
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| C-983-6 | 功能描述:烙鐵 PLUS SOLDERING TIP60 RoHS:否 制造商:Weller 產(chǎn)品:Soldering Stations 類型:Digital, Iron, Stand, Cleaner 瓦特:50 W 最大溫度:+ 850 F 電纜類型:US Cord Included |
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| C-983-7.5 | 功能描述:烙鐵 PLUS SOLDERING TIP75 RoHS:否 制造商:Weller 產(chǎn)品:Soldering Stations 類型:Digital, Iron, Stand, Cleaner 瓦特:50 W 最大溫度:+ 850 F 電纜類型:US Cord Included |
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