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參數(shù)資料
| 型號(hào)： | C9835CTT |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Low-EMI Clock Generator for Intel Mobile 133-MHz/3 SO-DIMM Chipset Systems |
| 中文描述： | 低電磁干擾時(shí)鐘發(fā)生器英特爾移動(dòng)133兆赫/ 3的SO - DIMM芯片系統(tǒng) |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 343K |
| 代理商： | C9835CTT |
C9835
Document #: 38-07303 Rev. **
Page 7 of 18
2-Wire SMBUS Control Interface
The 2-wire control interface implements a read/write slave
only interface according to SMBus specification. (See
Figure 5
below). The device can be read back by using standard
SMBUS command bytes. Sub addressing is not supported,
thus all preceding bytes must be sent in order to change one
of the control bytes. The 2-wire control interface allows each
clock output to be individually enabled or disabled. 100 Kbits/s
(standard mode) data transfer is supported.
During normal data transfer, the SDATA signal only changes
when the SCLK signal is low, and is stable when SCLK is high.
There are two exceptions to this. A high to low transition on
SDATA while SCLK is high is used to indicate the start of a data
transfer cycle. A low to high transition on SDATA while SCLK
is high indicates the end of a data transfer cycle. Data is
always sent as complete 8-bit bytes, after which an
acknowledge is generated. The first byte of a transfer cycle is
an 8-bit address. The LSB address Byte = 0 in write mode.
The device will respond to transfers of 10 bytes (max) of data.
The device will generate an acknowledge (low) signal on
SDATA following reception of each byte. Data is transferred
MSB first at a max rate of 100kbits/s. This device will also
respond to a D3 address which sets it in a read mode. It will
not respond to any other control interface conditions, and
previously set control registers are retained.
When a clock driver is placed in power down mode, the
SMBUS signals SDATA and SCLK must be tri-stated. In power
down, the device retains all SMBUS programming information.
CPU = 133.3MHz, SDRAM = 133.3MHz
Tolerance(ps)
500
500
500
500
1000
N/A
Offset(ns)
3.75
0
3.75
1.5
–
3.5
0
Async
Conditions
CPU to SDRAM/DCLK
CPU to 3V66
SDRAM/DCLK to 3V66
3V66 to PCI
PCI to IOAPIC
48M (0,1)
180 degrees phase shift
3V66 leads
Table 4. Group Timing Relationships and Tolerances
(continued)
CPU = 66.6 MHz, SDRAM = 100 MHz
START CONDITION
Transmit
Receive
STOP CONDITION
START CONDITION
Transmit
Receiv
STOP CONDITION
1
8
ACK
MSB
0
0
0
DATA
0
1
LSB
COMMAND BYTE
1
CLK
1
BYTE N
8
8
8
BYTE 0
BYTE COUNT
ACK
ACK
ACK
ACK
(Don
’
t Care)
(Don
’
t Care)
(Valid)
(Valid)
Figure 5a
(WRITE Cycle)
(Valid)
DATA
1
0
(Valid)
0
1
1
8
BYTE N
(Valid)
BYTE COUNT
CLK
LSB
ACK
8
ACK
ACK
8
0
BYTE1
1
ACK
ACK
MSB
8
1
(Valid)
BYTE 0
Figure 5b (READ Cycle)
Figure 5. SMBus Communications Waveforms
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| C9835CY | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Low-EMI Clock Generator for Intel Mobile 133-MHz/3 SO-DIMM Chipset Systems |
| C9835CYT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Low-EMI Clock Generator for Intel Mobile 133-MHz/3 SO-DIMM Chipset Systems |
| C-983-6 | 功能描述:烙鐵 PLUS SOLDERING TIP60 RoHS:否 制造商:Weller 產(chǎn)品:Soldering Stations 類型:Digital, Iron, Stand, Cleaner 瓦特:50 W 最大溫度:+ 850 F 電纜類型:US Cord Included |
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