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參數(shù)資料
| 型號： | C9630 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | PC133 Clock Generator for SiS630/Pentium III & SiS540/Socket7 Applications |
| 中文描述： | PC133的時鐘發(fā)生器SiS630/Pentium三 |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 185K |
| 代理商： | C9630 |
PC133 Clock Generator for SiS630/Pentium
III & SiS540/Socket7 Applications
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07035 Rev. **
05/02/2001
Page 7 of 18
APPROVED PRODUCT
C9630
Serial Control Registers (Cont.)
Byte 1: CPU Clock Register
(1 = enable, 0 = Stopped)
Bit
@Pup
Pin#
7
1
-
Description
Selects Frequency at pin 25
0 = selects 48MHz
SSTS, See Table 4, p 11
Reserved for IMI test^
Reserved for IMI test^
CPU2 enable/Stopped
CPU1 enable/Stopped
CPU0 enable/Stopped
Reserved for IMI test^
6
5
4
3
2
1
0
1
1
1
1
1
1
1
-
-
-
43
45
46
-
Byte 2: PCI Clock Register
(1 = enable, 0 = Stopped)
Bit
@Pup
Pin#
7
1
-
6
1
14
5
1
13
4
1
12
3
1
11
2
1
9
1
1
8
0
1
7
Description
Reserved
PCI6 enable/Stopped
PCI5 enable/Stopped
PCI4 enable/Stopped
PCI3 enable/Stopped
PCI2 enable/Stopped
PCI1 enable/Stopped
PCI0 enable/Stopped
Byte 3: SDRAM Clock Register
(1 = enable, 0 = Stopped)
Bit
@Pup
Pin#
7
1
32
6
1
31
5
1
29
4
1
28
3
1
21
2
1
20
1
1
18
0
1
17
Description
SDRAM7 enable/Stopped
SDRAM6 enable/Stopped
SDRAM5 enable/Stopped
SDRAM4 enable/Stopped
SDRAM3 enable/Stopped
SDRAM2 enable/Stopped
SDRAM1 enable/Stopped
SDRAM0 enable/Stopped
Byte 4: Additional SDRAM Clock Register
(1=enable, 0=Stopped)
Bit
@Pup
Pin#
Description
7
1
25
24_48MHz enable/Stopped
6
1
26
48 MHz enable/Stopped
5
1
41
SDRAM13 enable/Stopped
4
1
40
SDRAM12 enable/Stopped
3
1
38
SDRAM11 enable/Stopped
2
1
37
SDRAM10 enable/Stopped
1
1
35
SDRAM9 enable/Stopped
0
1
34
SDRAM8 enable/Stopped
Byte 5: Peripheral Control
(1 = enable, 0 = Stopped)
Bit
@Pup
Pin#
7
1
-
Description
MBS1
, See table 4, p. 11 for
Spread Spectrum
MBS0
, See table 4, p.11 for
Spread Spectrum
S3# *
S2# *
S1# *
S0# *
REF1 enable/Stopped
REF0 enable/Stopped
6
1
-
5
4
3
2
1
0
1
1
1
1
1
1
-
-
-
-
48
2
*
Inverted read back of hardware settings.
Byte 6: Reserved Register
(1 = enable, 0 = Stopped)
Bit
@Pup
Pin#
7
0
-
6
0
-
5
0
-
4
0
-
3
0
-
2
1
-
1
0
-
0
0
-
Description
Reserved for IMI test^
Reserved for IMI test^
Reserved for IMI test
Reserved for IMI test
N9, MSB
N8
Byte 7: Dial-a-Frequency
N Register
(1 = enable, 0 = Stopped)
Bit
@Pup
Pin#
Description
7
0
-
N7
6
0
-
N6
5
0
-
N5
4
0
-
N4
3
0
-
N3
2
0
-
N2
1
0
-
N1
0
0
-
N0, LSB
Byte 8: Dial-a-Frequency
R Register
(1 = enable, 0 = Stopped)
Bit
@Pup
Pin#
Description
7
0
-
R6, MSB
6
0
-
R5
5
0
-
R4
4
0
-
R3
3
0
-
R2
2
0
-
R1
1
0
-
R0, LSB
0
0
-
1 = Enable SMBus N and R
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