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參數(shù)資料
| 型號(hào)： | C9630 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | PC133 Clock Generator for SiS630/Pentium III & SiS540/Socket7 Applications |
| 中文描述： | PC133的時(shí)鐘發(fā)生器SiS630/Pentium三 |
| 文件頁(yè)數(shù)： | 4/18頁(yè) |
| 文件大?。?/td> | 185K |
| 代理商： | C9630 |
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PC133 Clock Generator for SiS630/Pentium
III & SiS540/Socket7 Applications
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07035 Rev. **
05/02/2001
Page 4 of 18
APPROVED PRODUCT
C9630
Power on Bi-Directional Pins
Power Up Condition:
Pins 2,7,8,and 26 are Power up bi-directional pins used for selecting the host frequency in page 1, table 1. During
power-up of the device, these pins are in input mode (see Fig 4, below), therefore; they are considered input select pins
internal to the IC. After a settling time, the selection data is latch into the internal control register and these pins become
a clock outputs.
-
Hi-Z Input
Toggle Outputs
ower Supply
amp
Select data is latched into register, then pin becomease ref clock output signal.
Fig.4
REF0 / S3
PCI0 / S1
PCI1 / S2
48MHZ / S0
VDD Rail
Strapping Resistor Options:
The power up bi-directional pins have a large value pull-
down each (250K
)
, therefore, a selection
“
0
”
is the
default. If the system uses a slow power supply (over
5mS settling time), then
it is recommended
to use an
external Pull-Down (Rdn) in order to insure a Low
selection. In this case, the designer may choose one of
two configurations, see Fig.5A and B.
Fig. 5A represents an additional pull down resistor Rdn
= 50K
connected from the pin to the ground plane,
which allows a faster pull to a low level.
If a selection
“
1
”
is desired, then a jumper is placed on
JP1 to a Rup = 10K
resistor as implemented as
shown in Fig.5A. Please note the selection resistors
(Rup and Rdn
)
are placed before the Damping resistor
(Rd) close to the pin.
Fig. 5B represent a single resistor 10K
connected to a
3-way jumper, JP2. When a
“
1
”
selection is desired, a
jumper is placed between leads1 and 3. When a
“
0
”
selection is desired, a jumper is placed between leads 3
and 2.
Fig.5A
Fig.5B
1
2
3
Load
Load
VDD
VDD
IMIC9630
Bidirectional
10K
50K
Rd
JP1
IMIC9630
Bidirectional
Rd
10K
JP2
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