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參數(shù)資料
| 型號(hào)： | C9630 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | PC133 Clock Generator for SiS630/Pentium III & SiS540/Socket7 Applications |
| 中文描述： | PC133的時(shí)鐘發(fā)生器SiS630/Pentium三 |
| 文件頁數(shù)： | 10/18頁 |
| 文件大?。?/td> | 185K |
| 代理商： | C9630 |
PC133 Clock Generator for SiS630/Pentium
III & SiS540/Socket7 Applications
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07035 Rev. **
05/02/2001
Page 10 of 18
APPROVED PRODUCT
C9630
SMBus Test Circuitry
Fig.7
Note: Buffer is 7407 with VCC @ 5.0 V
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is a modulation technique applied here for maximum efficiency in minimizing Electro-Magnetic
Interference radiation generated from repetitive digital signals mainly clocks. A clock accumulates EM energy at the
center frequency it is generating. Spread Spectrum distributes this energy over a small frequency bandwidth therefore
spreading the same amount of energy over a spectrum. This technique is achieved by modulating the clock down from
(Fig.8A) or around the center (Fig.8B) of its resting frequency by a certain percentage (which also determines the
energy distribution bandwidth). In this device, Spread Spectrum is enabled by setting I
2
C byte0, bit1 = 1. The default of
the device at power up keeps the Spread Spectrum disabled, it is therefore, important to have I
2
C accessibility to turn-on
the Spread Spectrum function. Once the Spread Spectrum is enabled, the spread bandwidth option is selected by
MBS(0:1) in I
2
C byte 5, bit6 and bit 7, and SSTS Byte1, Bit6 following table 4 below.
In Down Spread mode the center frequency is shifted down from its rested (non-spread) value by
of the total spread
%. (eg.: assuming the center frequency is 100MHz in non-spread mode; when down spread of
–
0.5% is enabled, the
center frequency shifts to 99.75MHz.).
2.2 K
Device under Test
SDATA
DATAIN
SCLK
DATAOUT
CLOCK
+ 5V
+ 5V
+ 5V
2.2 K
2.2 K
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