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參數(shù)資料
| 型號(hào)： | C8051F010 |
| 廠商： | Cygnal Technologies |
| 英文描述： | 20 MIPS,32k Flash,256 Ram,10bit ADC,64 Pin MCU(20 MIPS,32k 閃速存儲(chǔ)器,256 Ram,10位 ADC,64 腳 MCU) |
| 中文描述： | 20 MIPS的，32K閃存，256羊，10位ADC，64引腳微控制器（20 MIPS的，32K的閃速存儲(chǔ)器，256，羊，10位ADC和64腳微控制器） |
| 文件頁數(shù)： | 102/170頁 |
| 文件大?。?/td> | 1294K |
| 代理商： | C8051F010 |
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Page 102
CYGNAL Integrated Products, Inc.
2001
4.2001; Rev. 1.3
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
PRELIMINARY
15. PORT INPUT/OUTPUT
The MCUs have a wide array of digital resources, which are available through four digital I/O ports, P0, P1, P2 and
P3. Each of the pins on Ports 0, 1, and 2 can be defined as either its corresponding port I/O or one of the internal
digital resources assigned as shown in Figure 15.1. The designer has complete control over which functions are
assigned, limited only by the number of physical I/O pins available on the selected package (the
C8051F000/05/10/15 have all four ports pinned out, the F001/06/11/16 have P0 and P1, and the F002/07/12/17 have
P0). This resource assignment flexibility is achieved through the use of a Priority CrossBar Decoder. (Note that the
state of a Port I/O pin can always be read in the corresponding Port latch regardless of the Crossbar settings).
The CrossBar assigns the selected internal digital resources to the I/O pins based on the Priority Decode Table 15.1.
The registers XBR0, XBR1, and XBR2, defined in Figure 15.3, Figure 15.4, and Figure 15.5 are used to select an
internal digital function or let an I/O pin default to being a Port I/O. The crossbar functions identically for each
MCU, with the caveat that P2 is not pinned out on the F001/06/11/16, and both P1 and P2 are not pinned out on the
F002/07/12/17. Digital resources assigned to port pins that are not pinned out cannot be accessed.
All Port I/Os are 5V tolerant (Refer to Figure 15.2 for the port cell circuit.) The Port I/O cells are configured as
either push-pull or open-drain in the Port Configuration Registers (PRT0CF, PRT1CF, PRT2CF, PRT3CF).
Complete Electrical Specifications for Port I/O are given in Table 15.2.
15.1.
Priority Cross Bar Decoder
One of the design goals of this MCU family was to make the entire palette of digital resources available to the
designer even on reduced pin count packages. The Priority CrossBar Decoder provides an elegant solution to the
problem of connecting the internal digital resources to the physical I/O pins.
The Priority CrossBar Decode (Table 15.1) assigns a priority to each I/O function, starting at the top with the
SMBus. As the table illustrates, when selected, its two signals will be assigned to Pin 0 and 1 of I/O Port 0. The
decoder always fills I/O bits from LSB to MSB starting with Port 0, then Port 1, finishing if necessary with Port 2. If
you choose not to use a resource, the next function down on the table will fill the priority slot. In this way it is
possible to choose only the functions required by the design, making full use of the available I/O pins. Also, any
extra Port I/O are grouped together for more convenient use in application code.
Registers XBR0, XBR1 and XBR2 are used to assign the digital I/O resources to the physical I/O Port pins. It is
important to understand that when the SMBus, SPI Bus, or UART is selected, the crossbar assigns all pins associated
with the selected bus. It would be impossible for instance to assign the RX pin from the UART function without also
assigning the TX function. Standard Port I/Os appear contiguously after the prioritized functions have been
assigned. For example, if you choose functions that take the first 14 Port I/O (P0.[7:0], P1.[5:0]), you would have 18
Port I/O left unused by the crossbar (P1.[7:6], P2 and P3).
15.2.
Port I/O Initialization
Port I/O initialization is straightforward. Registers XBR0, XBR1 and XBR2 must be loaded with the appropriate
values to select the digital I/O functions required by the design. Setting the XBARE bit in XBR2 to 1 enables the
CrossBar.
Until the Crossbar is enabled, the external pins remain as standard Ports in input mode regardless
of the XBRn Register settings.
For given XBRn Register settings, one can determine the I/O pin-out using the
Priority Decode Table; as an alternative, the Code Configuration Wizard function of the IDE software will determine
the Port I/O pin-assignments based on the XBRn Register settings.
The output driver characteristics of the I/O pins are defined using the Port Configuration Registers PRT0CF,
PRT1CF, PRT2CF and PRT3CF (see Figure 15.7, Figure 15.9, Figure 15.12, and Figure 15.14). Each Port Output
driver can be configured as either Open Drain or Push-Pull. This is required even for the digital resources selected
in the XBRn registers and is not automatic. The only exception to this is the SMBus (SDA, SCL) and UART
Receive (RX, when in mode 0) pins which are Open-drain regardless of the PRTnCF settings. When the
WEAKPUD bit in XBR2 is 0, a weak pullup is enabled for all Port I/O configured as open-drain. WEAKPUD does
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