參數(shù)資料
型號(hào): C8051F000
廠商: Cygnal Technologies
英文描述: 20 MIPS,32k Flash,256 Ram,12bit ADC,64 Pin MCU(20 MIPS,32k 閃速存儲(chǔ)器,256 Ram,12位 ADC,64 腳 MCU)
中文描述: 20 MIPS的,32K閃存,256羊,12位ADC,64引腳微控制器(20 MIPS的,32K的閃速存儲(chǔ)器,256,羊,12位ADC和64腳微控制器)
文件頁數(shù): 18/170頁
文件大小: 1294K
代理商: C8051F000
Page 18
CYGNAL Integrated Products, Inc.
2001
4.2001; Rev. 1.3
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
PRELIMINARY
1.7.
The C8051F000/1/2/5/6/7 has an on-chip 12-bit SAR ADC with a 9-channel input multiplexer and programmable
gain amplifier. With a maximum throughput of 100ksps, the ADC offers true 12-bit accuracy with an INL of
±
1LSB.
The ADC in the C8051F010/1/2/5/6/7 is similar, but with 10-bit resolution. Each ADC has a maximum throughput
of 100ksps. Each ADC has an INL of
±
1LSB, offering true 12-bit accuracy with the C8051F00x, and true 10-bit
accuracy with the C8051F01x. There is also an on-board 15ppm voltage reference, or an external reference may be
used via the VREF pin.
The ADC is under full control of the CIP-51 microcontroller via the Special Function Registers. One input channel
is tied to an internal temperature sensor, while the other eight channels are available externally. Each pair of the
eight external input channels can be configured as either two single-ended inputs or a single differential input. The
system controller can also put the ADC into shutdown to save power.
A programmable gain amplifier follows the analog multiplexer. The gain can be set in software from 0.5 to 16 in
powers of 2. The gain stage can be especially useful when different ADC input channels have widely varied input
voltage signals, or when it is necessary to “zoom in” on a signal with a large DC offset (in differential mode, a DAC
could be used to provide the DC offset).
Conversions can be started in four ways; a software command, an overflow on Timer 2, an overflow on Timer 3, or
an external signal input. This flexibility allows the start of conversion to be triggered by software events, external
HW signals, or convert continuously. A completed conversion causes an interrupt, or a status bit can be polled in
software to determine the end of conversion. The resulting 10 or 12-bit data word is latched into two SFRs upon
completion of a conversion. The data can be right or left justified in these registers under software control.
Compare registers for the ADC data can be configured to interrupt the controller when ADC data is within a
specified window. The ADC can monitor a key voltage continuously in background mode, but not interrupt the
controller unless the converted data is within the specified window.
Analog to Digital Converter
Figure 1.10. ADC Diagram
100ksps
SAR
ADC
+
-
Control & Data
SFR's
SFR Bus
+
-
+
-
+
-
9-to-1
AMUX
(SE or
DIFF)
+
-
X
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
TEMP
SENSOR
Programmable
Gain Amp
VREF
REF
(not bonded out on
F002, F007, F012,
and F017
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