參數(shù)資料
型號： C8051F000
廠商： Cygnal Technologies
英文描述： 20 MIPS,32k Flash,256 Ram,12bit ADC,64 Pin MCU(20 MIPS,32k 閃速存儲器,256 Ram,12位 ADC,64 腳 MCU)
中文描述： 20 MIPS的，32K閃存，256羊，12位ADC，64引腳微控制器（20 MIPS的，32K的閃速存儲器，256，羊，12位ADC和64腳微控制器）
文件頁數(shù)： 117/170頁
文件大?。?/td> 1294K
代理商： C8051F000
4.2001; Rev. 1.3
CYGNAL Integrated Products, Inc.
2001
Page 117
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
PRELIMINARY
Figure 16.4. SMB0CN: SMBus Control Register
R
R/W
ENSMB
Bit6
R/W
STA
Bit5
R/W
STO
Bit4
R/W
SI
Bit3
R/W
AA
Bit2
R/W
FTE
Bit1
R/W
TOE
Bit0
Reset Value
00000000
SFR Address:
0xC0
BUSY
Bit7
(bit addressable)
Bit7:
Bit6:
BUSY: Busy Status Flag.
0: SMBus is free
1: SMBus is busy
ENSMB: SMBus Enable.
This bit enables/disables the SMBus serial interface.
0: SMBus disabled.
1: SMBus enabled.
STA: SMBus Start Flag.
0: No START condition is transmitted.
1: When operating as a master, a START condition is transmitted if the bus is free. (If the
bus is not free, the START is transmitted after a STOP is received.) If STA is set after one
or more bytes have been transmitted or received and before a STOP is received, a repeated
START condition is transmitted.
STO: SMBus Stop Flag.
0: No STOP condition is transmitted.
1: Setting STO to logic 1 causes a STOP condition to be transmitted. When a STOP
condition is received, hardware clears STO to logic 0. If both STA and STO are set, a
STOP condition is transmitted followed by a START condition. In slave mode, setting the
STO flag causes SMBus to behave as if a STOP condition was received.
SI: SMBus Serial Interrupt Flag.
This bit is set by hardware when one of 27 possible SMBus states is entered. (Status code
0xF8 does not cause SI to be set.) When the SI interrupt is enabled, setting this bit causes
the CPU to vector to the SMBus interrupt service routine. This bit is not automatically
cleared by hardware and must be cleared by software.
AA: SMBus Assert Acknowledge Flag.
This bit defines the type of acknowledge returned during the acknowledge cycle on the SCL
line.
0: A “not acknowledge” (high level on SDA) is returned during the acknowledge cycle.
1: An “acknowledge” (low level on SDA) is returned during the acknowledge cycle.
FTE: SMBus Free Timer Enable Bit
0: No timeout when SCL is high
1: Timeout when SCL high time exceeds limit specified by the SMB0CR value.
TOE: SMBus Timeout Enable Bit
0: No timeout when SCL is low.
1: Timeout when SCL low time exceeds limit specified by Timer 3, if enabled.
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
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