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參數(shù)資料
| 型號(hào)： | BW2006L |
| 英文描述： | Rad-hard quad 2-input NAND gate |
| 中文描述： | BW2006L 100MHz的?500MHz的FSPLL BW2006L |數(shù)據(jù)資料 |
| 文件頁數(shù)： | 8/8頁 |
| 文件大?。?/td> | 814K |
| 代理商： | BW2006L |
100MHz~500MHz FSPLL
BW2006L
We appreciate your interest in our products. If you have further questions, please specify in
the attached form. Thank you very
much.
Parameter
Min
Typ
Max
Unit
Remarks
Supply Voltage
Output frequency range
Input frequency range
Cycle to Cycle Jitter
Lock up time
Dynamic current
Stand by current
Output clock duty ratio
Long term jitter
Output slew rate
- Do you need XTAL driver buffer in PLL Core
If you need it, what's the crystal frequency range If not, What's the input frequency range
- Do you need the lock detector
- Do you need the I/O cell of SEC
- Do you need the external pin for PLL test
- What's the main frequency & frequency range
- How many FSPLLs do you use in your system
- What's output loading
- Could you external/internal pin configurations as required
Specially requested function list :
PLL Specification
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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