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參數資料
| 型號： | BW2011L |
| 英文描述： | Rad-hard quad 2-input NOR gate |
| 中文描述： | BW2011L為20MHz?100MHz的FSPLL BW2011L |數據資料 |
| 文件頁數： | 1/5頁 |
| 文件大?。?/td> | 54K |
| 代理商： | BW2011L |
IN A.G.P.-2X Mode, the PLL output Frequency is
133
Frequency.
The PLL produces a good clock duty cycle with the
voltage controlled oscillator (VCO) running
266
The 133
outputs of the interface and proper care needs to be
taken such
that
the clock skew across the
interface is minimized.
1
/
3
Mhz which is doubled with 66
2
/
3
Mhz Input
at
2
/
3
MHz and divide by 2.
1
/
3
MHz clock also has to be routed to all
* 66
2
/
3
= 66.66MHz
133
1
/
3
= 133.33MHz
266
2
/
3
= 266.66MHz
. 0.35u CMOS device technology
. Single power supply : +3.3V
. Output frequency : 133
1
/
3
MHz
. Jitter : +/- 100ps
. Duty ratio : 49% to 51%
. Provision for 66
2
/
3
MHz Input frequency.
. Power Down mode
General Description
Features
Functional Block
Diagram
PFD
Charge
Pump
VCO
Loop
Filter
External
VDD
VSS
VDDA
VSSA
VBB
FIN
FILTER
FOUT2X
PWRDN
Figure1 . Functional Block Diagram
1/2
Buffer
1/2
Buffer
FOUT
VSUB
Frequency Doubler
BW2010AGP
DECEMBER 1998. Ver1.0
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