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參數(shù)資料
| 型號(hào)： | BW2006L |
| 英文描述： | Rad-hard quad 2-input NAND gate |
| 中文描述： | BW2006L 100MHz的?500MHz的FSPLL BW2006L |數(shù)據(jù)資料 |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大小： | 814K |
| 代理商： | BW2006L |
100MHz~500MHz FSPLL
BW2006L
NAME
I/O
TYPE
I/O PAD
PIN DESCRIPTION
VDD
DP
vddd
Digital power supply
VSS
DG
vssd
Digital ground
VDDA
AP
vdda
Analog power supply
VSSA
AG
vssa
Analog ground
VBB/VSUB
AG
vbba
Substrate ground
FIN
DI
picc_bb
PLL clock input
FILTER
AO
poa50r_bb
. Pump out is connected to Filter
. A capacitor is connected between the pin
and analog ground
FOUT
DO
pot12_bb or
Special Buffer
100MHz~500MHz clock output
need special drive buffer
PWRDN
AI
picc_bb
PLL power down.(Active High)
-If isn't used this pin, tied to VSSA.
P[5:0]
DI
picc_bb
The values for 6bit programmable pre-divider.
M[5:0]
DI
picc_bb
The values for 6bit programmable main divider.
S[1:0]
DI
picc_bb
The values for 2bit programmable post scaler.
CORE PIN DESCRIPTION
I/O TYPE ABBR.
AI : Analog Input
DI : Digital Input
AO : Analog Output
DO : Analog Output
AP : Analog Power
AG : Analog Ground
AB : Analog Sub Bias
DP : Digital Power
DG : Digital Ground
DB : Digital Sub Bias
BD : Bidirectional Port
CORE CONFIGURATION
FIN
PWRDN
M[0]
M[1]
M[2]
M[3]
M[4]
M[5]
P[0]
P[1]
P[2]
P[3]
P[4]
P[5]
S[0]
S[1]
FOUT
FILTER
BW2006L
M[5:0]
P[5:0]
S[1:0]
Figure2.
Core configuration
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