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參數(shù)資料
| 型號(hào)： | BW2006L |
| 英文描述： | Rad-hard quad 2-input NAND gate |
| 中文描述： | BW2006L 100MHz的?500MHz的FSPLL BW2006L |數(shù)據(jù)資料 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 814K |
| 代理商： | BW2006L |
100MHz~500MHz FSPLL
BW2006L
Functional Description
A PLL is circuit synchronizing an feedback signal (divided down after generated by an VCO) with a
reference or
input signal in frequency as well as phase.
In this application, it includes following basic blocks.
. A voltage-controlled oscillator to generate the output frequency
. A divider P to devide down the reference frequency
. A divider M to devide down the VCO output frequency
. A divider S to divide
down the VCO output frequency
. A phase detector to detect the phase difference
between the reference frequency and the output frequency (after divide down)
and control the charge pump voltage.
. A loop filter to filter out the high frequency in charge pump voltage and give
smooth and clean control to VCO
by p
by m
by s
The m, p, s values can be programmed by
So, the PLL can be locked in the frequency we want.
14bit digital data from the external
source.
FOUT = m *8* FIN / p*s
Where,
m=M+2 , p=P+2, s=2^S
NOTES
. S1 -
. M5 - M0 : VCO Frequency Divider
. P5
- P0 : Reference Frequency Input Divider
S0 : Output Frequency Scaler
Main Divider Pin
Pre Divider Pin
Post Scaler Pin
M5,M4,M3,M2,M1,M0
P5,P4,P3,P2,P1,P0
S0,S1
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