參數(shù)資料
型號(hào): BUK9775-56
廠商: NXP Semiconductors N.V.
英文描述: TrenchMOS(TM)transistor Logic level FET(TrenchMOS(TM)晶體管邏輯電平FET)
中文描述: TrenchMOS(商標(biāo))場效應(yīng)晶體管邏輯電平(TrenchMOS(商標(biāo))晶體管邏輯電平場效應(yīng)管)
文件頁數(shù): 1/8頁
文件大?。?/td> 68K
代理商: BUK9775-56
Philips Semiconductors
Product specification
TrenchMOS
transistor
Logic level FET
BUK9775-55
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode logic
level field-effect power transistor in a
plastic
full-pack
trench
’ technology.
featuresverylow on-state resistance
and has integral zener diodes giving
ESD protection up to 2kV. It is
intended for use in automotive and
general
purpose
applications.
SYMBOL
PARAMETER
MAX.
UNIT
envelope
The
using
device
V
DS
I
D
P
tot
T
j
R
DS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
55
11.7
19
150
75
V
A
W
C
m
V
GS
= 5 V
switching
PINNING - SOT186A
PIN CONFIGURATION
SYMBOL
PIN
DESCRIPTION
1
gate
2
drain
3
source
case isolated
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
V
DGR
±
V
GS
I
D
I
D
I
DM
P
tot
T
stg
, T
j
PARAMETER
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
CONDITIONS
-
R
GS
= 20 k
-
T
mb
= 25 C
T
mb
= 100 C
T
mb
= 25 C
T
mb
= 25 C
-
MIN.
-
-
-
-
-
-
-
- 55
MAX.
55
55
10
11.7
7.4
47
19
150
UNIT
V
V
V
A
A
A
W
C
ESD LIMITING VALUE
SYMBOL
V
C
PARAMETER
Electrostatic discharge capacitor
voltage, all pins
CONDITIONS
Human body model
(100 pF, 1.5 k
)
MIN.
-
MAX.
2
UNIT
kV
THERMAL RESISTANCES
SYMBOL
R
th j-mb
PARAMETER
Thermal resistance junction to
heatsink
Thermal resistance junction to
ambient
CONDITIONS
with heatsink compound
TYP.
-
MAX.
6.5
UNIT
K/W
R
th j-a
in free air
55
-
K/W
d
g
s
1 2 3
case
April 1998
1
Rev 1.000
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參數(shù)描述
BUK98150-55 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:TrenchMOS transistor Logic level FET
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