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參數(shù)資料
| 型號(hào)： | BU3076HFV-TR |
| 廠商： | Rohm Semiconductor |
| 文件頁(yè)數(shù)： | 8/22頁(yè) |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 1CH HVSOF6 |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 類(lèi)型： | 時(shí)鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | 數(shù)碼相機(jī) |
| 輸入： | 時(shí)鐘 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 67.5MHz |
| 電源電壓： | 2.85 V ~ 3.6 V |
| 工作溫度： | -5°C ~ 75°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 6-SMD |
| 供應(yīng)商設(shè)備封裝： | HVSOF6 |
| 包裝： | 帶卷 (TR) |
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16
DS601F2
CS5340
Confidential Draft
3/11/08
4.2.1
Operation as a Clock Master
As a clock master, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally de-
rived from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as
shown in Figure 18.
4.2.2
Operation as a Clock Slave with Auto-Detect
LRCK and SCLK operate as inputs in clock slave mode. It is recommended that the left/right clock be
synchronously derived from the master clock and must be equal to Fs. It is also recommended that the
serial clock be synchronously derived from the master clock and be equal to 64x Fs to maximize system
performance.
A unique feature of the CS5340 is the automatic selection of either Single-, Double- or Quad-Speed mode
when operating as a clock slave. The auto-mode select feature negates the need to configure the Mode
pins to correspond to the desired mode. The auto-mode selection feature supports all standard audio
sample rates from 2 to 200 kHz. However, there are ranges of non-standard audio sample rates that are
not supported when operating with a fast MCLK (512x, 256x, 128x for Single-, Double-, and Quad-Speed
Modes, respectively). Please refer to Table for supported sample rate ranges.
÷ 128
÷ 256
÷ 64
M0
M1
LRCK Output
(Equal to Fs)
Single
Speed
Quad
Speed
Double
Speed
00
01
10
÷ 2
÷ 4
÷ 1
SCLK Output
Single
Speed
Quad
Speed
Double
Speed
00
01
10
÷ 2
÷ 1
0
1
MCLK
Auto-Select
Figure 18. CS5340 Master Mode Clocking
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