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參數(shù)資料
| 型號(hào)： | BU3076HFV-TR |
| 廠商： | Rohm Semiconductor |
| 文件頁數(shù)： | 7/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 1CH HVSOF6 |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 類型： | 時(shí)鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | 數(shù)碼相機(jī) |
| 輸入： | 時(shí)鐘 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 67.5MHz |
| 電源電壓： | 2.85 V ~ 3.6 V |
| 工作溫度： | -5°C ~ 75°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 6-SMD |
| 供應(yīng)商設(shè)備封裝： | HVSOF6 |
| 包裝： | 帶卷 (TR) |
DS601F2
15
CS5340
Confidential Draft
3/11/08
4. APPLICATIONS
4.1
Single-, Double-, and Quad-Speed Modes
The CS5340 can support output sample rates from 2 kHz to 200 kHz. The proper speed mode can be de-
termined by the desired output sample rate and the external MCLK/LRCK ratio, as shown in Table 1.
Table 1. Speed Modes and the Associated Output Sample Rates (Fs)
4.2
Operation as Either a Clock Master or Slave
The CS5340 supports operation as either a clock master or slave. As a clock master, the LRCK and SCLK
pins are outputs with the left/right and serial clocks synchronously generated on-chip. As a clock slave, the
LRCK and SCLK pins are inputs and require the left/right and serial clocks to be externally generated. The
selection of clock master or slave is made via the Mode pins as shown in Table 2.
Speed Mode
MCLK/LRCK
Ratio
Output Sample Rate Range (kHz)
Single-Speed Mode
512x
43 - 50
256x
2 - 50
Double-Speed Mode
256x
86 - 100
128x
4 - 100
Quad-Speed Mode
128x
172 - 200
64x*
100 - 200
* Quad-Speed Mode, 64x only available in Master Mode.
M1 (Pin 16)
M0 (Pin 1)
MODE
00
Clock Master, Single-Speed Mode
01
Clock Master, Double-Speed Mode
10
Clock Master, Quad-Speed Mode
11
Clock Slave, All Speed Modes
Table 2. CS5340 Mode Control
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