
Bt2166
Graphics/Video Controller
Brooktree
110
GUI ACCELERATOR
CPU Addressing of GUI
L2166_A
Notice in Table 76 that register accesses occupy the rst 64 KB of the GUI ac-
cess space. This is the queued method of register access described above in which
register loads are guaranteed to behave in strict sequential order with respect to the
drawing operations. The register access commands are repeated at GBASE+4MB
where they are not queued (a register write will occur immediately regardless of
whether the accelerator is busy or idle). It is generally too dangerous to access GUI
accelerator registers using the non-queued address space while the accelerator is
busy.
The non-queued method is used for various non-accelerator registers, which are
dened in “BIOS ROM Support” on page 23 of the “CPU Address Space Aper-
tures” chapter. The non-queued GUIREG_MBA register controls the type of bit,
byte, word, and dword ipping occurs throughout the ippin map of the protected
mode aperture and is relatively unrelated to GUI accelerator command queueing.
However during driver initialization, this register is loaded with a value that con-
trols whether GUI commands/register/data access are big endian or little endian.
Shown in Table 76, a bit eld is reserved within both drawing operation ad-
dresses and data word transfer addresses so that addresses from a REP MOVSD in-
struction can “roll” through the parameters. Thus you can keep the basic command
address in the program, load it into EDI (a 32-bit offset register), then pass out 8K
dwords of host-to-screen BLT data using the ADDRESS ROLL eld. Thus a draw-
ing command could be started at any one of eight possible addresses correspond-
ing to one of the values of the PARAMETER ADDRESS ROLL FIELD.
Whether a dword is a command or a parameter is not encoded in this eld. The
two are distinguished by their placement in the transfer sequence relative to the
previously issued command. Every dword comes over the bus in one cycle and
contains an address and a data eld. The rst parameter (if any) accompanies the
rst address eld. For example, if a drawing command was issued with parameter
count 2, the next command of whatever type will appear as the second dword fol-
lowing the drawing command.
Table 76. Address Fields For GUI Accesses
CPU Address
Bits
Field Description
GUI Selector #
Register Access
CPU-GUI Data Transfers
Drawing Operations
21:16
GUI Command Number =
6’b000000
GUI Command Number =
6’b000001
GUI Command Number > 6’b000001
15:14
Unused
1-16 K Data dword
address roll eld
Reserved
13:11
Source Bitmap Selector for 2D opera-
tions. (1)
10:8
Destination Bitmap Selector, 2D opera-
tions(1)
7:5
Register Number
Parameter Count
4:2
Parameter Address Roll Field
1:0
Always set to zero, i.e. a 32-bit transfer
(1). See Table 86, “Bitmap Context Registers,” on page 120