
Bt2166
Graphics/Video Controller
Brooktree
326
CPU HOST BUS INTERFACE
PCI/AGP Local Bus Interface
L2166_A
PCI/AGP Functionality
The Bt2166 is a 66MHz device designed to attach to either a PCI bus running up
to 33MHz or an AGP bus running at 66MHz (using AGP timings). In all cases, the
Bt2166 performs as a PCI device; however, its ability to operate at 66MHz enables
it to function in an AGP bus environment. The Bt2166 implements only the AGP
functionality that is part of the PCI Local Bus Specication, Revision 2.1. It does
not implement any of the AGP New Capabilities Registers.
PCI Address and Data
Bus
PCI_AD[31:0]—These tri-state, bi-directional, IO pins handle both address and
data information. A bus transaction consists of an address phase followed by one
or more data phases for either read or write operations.
The address phase is the clock cycle in which PCI_FRAME is rst asserted.
During the address phase, PCI_AD[31:0] contains a byte address for IO operations
or a dword address for conguration and memory operations. During data phases,
PCI_AD[7:0] contains the least signicant byte and PCI_AD[31:24] contains the
most signicant byte.
Read data is stable and valid when PCI_TRDY is asserted; write data is stable
and valid when PCI_IRDY is asserted. Data is transferred during the clocks when
both PCI_TRDY and PCI_IRDY are asserted.
PCI Bus Command and
Byte Enables
PCI_C_BE[3:0]—These tri-state, bidirectional, IO pins handle both bus command
and byte enable information. During the address phase of a transaction,
PCI_C_BE[3:0] contain the bus command. During the data phase, PCI_C_BE[3:0]
are used as byte enables. The byte enables are valid for the entire data phase and
determine which byte lanes carry meaningful data. PCI_C_BE[3] refers to the
most signicant byte and PCI_C_BE[0] refers to the least signicant byte.
PCI Parity
PCI_PAR—This tri-state, bidirectional, IO pin provides even parity across
PCI_AD[31:0] and PCI_C_BE[3:0]. This means that the number of 1’s on
PCI_PAR, PCI_AD[31:0], and PCI_C_BE[3:0] equals an even number.
PCI_PAR is stable and valid one clock after the address phase. For data phases,
PCI_PAR is stable and valid one clock after either PCI_TRDY is asserted on a
read or PCI_IRDY is asserted on a write. Once valid, PCI_PAR remains valid until
one clock after the completion of the current data phase. PCI_PAR and
PCI_AD[31:0] have the same timing, but PCI_PAR is delayed by one clock. For
any transaction, the target drives PCI_PAR for read data phases; the master drives
PCI_PAR for address and write data phases.
PCI Clock
PCI_CLK—This input provides timing for all PCI transactions. All PCI signals
except PCI_RST and the optional interrupt are sampled on the rising edge of
PCI_CLK, and all other timing parameters are dened with respect to this edge.
The Bt2166 supports a PCI clock of up to 66MHz.
PCI Reset
PCI_RST—This input resets all functions on the Bt2166 before execution.
PCI_RST may be asynchronous to PCI_CLK when asserted or deasserted.
PCI Cycle Frame
PCI_FRAME—This sustained tri-state signal is driven by the current master to in-
dicate the beginning and duration of an access. PCI_FRAME is asserted to signal
the beginning of a bus transaction. Data transfer continues throughout assertion. At
deassertion, the transaction is in the nal data phase.