
Brooktree
291
3D GRAPHICS ACCELERATOR
PRE Programming
L2166_A
Bt2166
Graphics/Video Controller
PRE Programming
The PRE pipeline performs a sequence of operations that are designed to perform the
most complex rendering algorithm, namely perspective texture mapped polygon ren-
dering. Other algorithms are special cases of this algorithm.
In order to draw a polygon in the screen buffer, it is rst broken down into a set of
stripes, one pixel wide; this process is known as scan conversion. Some of this process
is performed in software on the TSC, which passes a set of triangle parameters, calcu-
lated during the setup phase, to PRE, which then draws the triangle in the screen buffer.
The calculations that are required for each pixel are always the same, and always oc-
cur in the same order. Therefore, PRE is arranged as a series of stages (a 'pipeline'),
each of which performs one stage of the calculation; the output of each stage is latched
or stored in a FIFO RAM before it is passed to the next stage. The throughput of the
pipeline is therefore one pixel per PRE clock cycle, although it takes several cycles for
an individual pixel to be calculated. Because several pixels are being calculated at
once, some care must be taken to change PRE parameters at the correct time.
Initialization and
Default Value Set-up
The MODE register is cleared to 0 after a hardware reset. However, the working and in-
crement registers would generally be set up on a per triangle basis anyway and actually
reset to the undened state. To put PRE into a state where all functions are disabled all
registers should be set up with their recommended initialization value. Of particular
note, when using texture maps the QVAL register must be initialized correctly to dis-
able perspective correction.
Starting Under normal circumstances, all parameter registers must be reset for each new trian-
gle. If this is not done, on the new span, all such parameters will actually take on the
previous span start values.
Pixel Output The nal pixel color must be written to the correct position in the screen buffer.The ad-
dress is calculated by adding an increment, derived from the pixel size and screen
width, to a base address at each PRE step.
Before the pixel value may be written to the screen, it is formatted. The calculated
pixel value consists of three eight bit precision color values, so the RGB888 value is
truncated to RGB565 or RGB332 for 16 bit or 8 bit modes respectively. The truncation
process chops off the bottom bits of the color values, i.e. for 16 bit color, Red and Green
lose the bottom 3 bits and Green loses the bottom 2 bits.
The pixel values are not written directly to the screen. When each pixel is sixteen
bits wide, and is generally adjacent to the previous pixel, the utilization of the bus band-
width may be minimized by performing the screen writes in bursts. The pixel values are
therefore written to a pixel buffer, which stores the values until they are written out by
the memory controller (see Figure 54).