參數(shù)資料
型號(hào): BR93LC46-W
廠商: Rohm CO.,LTD.
英文描述: 64】16bits serial EEPROM
中文描述: 64串行EEPROM】16位
文件頁數(shù): 9/11頁
文件大?。?/td> 94K
代理商: BR93LC46-W
BR93LC46-W / BR93LC46F-W / BR93LC46RF-W /
Memory ICs
BR93LC46FJ-W / BR93LC46RFJ-W / BR93LC46FV-W
(2) Timing in the standby mode
As shown in Fig.16, during standby, if CS rises when SK is HIGH, the DI state may be read on the rising edge. If this
happens, and DI is HIGH, this is taken to be the start bit, causing a bit error (see point “a” in Fig.16).
Make sure all inputs are LOW during standby or when turning the power supply on or off (see Fig.17).
SK
CS
DI
a
b
0
1
Point a: Start bit position during erroneous operation
Point b: Timing during normal operation
Fig. 16 Erroneous operation timing
SK
CS
DI
0
1
b
Fig. 17 Normal operation timing
(3) Precautions when turning power on and off
When turning the power supply on and off, make sure CS is set to LOW (see Fig.18).
When CS is HIGH, the EEPROM enters the active state. To avoid this, make sure CS is set to LOW (disable mode)
when turning on the power supply. (When CS is LOW, all input is cancelled.)
When the power supply is turned off, the low power state can continue for a long time because of the capacity of the
power supply line. Erroneous operations and erroneous writing can occur at such times for the same reasons as
described above. To avoid this, make sure CS is set to LOW before turning off the power supply.
To prevent erroneous writing, these ICs are equipped with a POR (Power On Reset) circuit, but in order to achieve
operation at a low power supply, V
CC
is set to operate at approximately 1.3V. After the POR has been activated,
writing is disabled, but if CS is set to HIGH, writing may be enabled because of noise or other factors. However, the
POR circuit is effective only when the power supply is on, and will not operate when the power is off.
Also, to prevent erroneous writing at low voltages, these ICs are equipped with a built-in circuit (V
CC
-lockout circuit)
which resets the write command if V
CC
drops to approximately 2V or lower (typ.) (
).
Good example
Bad example
GND
+
5V
GND
+
5V
V
CC
CS
Fig. 18
Here, the CS pin is pulled up to V
CC
. In this case,
CS is HIGH (active state). Please be aware that the EEPROM may
perform erroneous operations or write erroneous data because of
noise or other factors. Please be aware that this can occur even if
the CS input is HIGH-Z.
In this case, CS is LOW when the power supply is turned
on or off.
(Bad example)
(Good example)
(4) Clock (SK) rise conditions
If the clock pin (SK) signal of the BR93LC46-W has a long rise time (tr) and if noise on the signal line exceeds a
certain level, erroneous operation can occur due to erroneous counts in the clock. To prevent this, a Schmitt trigger is
built into the SK input of the BR93LC46-W. The hysteresis amplitude of this circuit is set to approximately 0.2V, so if
the noise exceeds the SK input, the noise amplitude should be set to 0.2V
P-P
or lower. Furthermore, rises and falls in
the clock input should be accelerated as much as possible.
相關(guān)PDF資料
PDF描述
BR93LC46F-W 64】16bits serial EEPROM
BR93LC46FJ-W 64】16bits serial EEPROM
BR93LC46RFJ-W 64】16bits serial EEPROM
BRT1A Quad Differential Receivers(四差分接收器)
BRF1A Quad Differential Receivers(四差分接收器)
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