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參數(shù)資料
| 型號： | BR93LC46-W |
| 廠商： | Rohm CO.,LTD. |
| 英文描述： | 64】16bits serial EEPROM |
| 中文描述： | 64串行EEPROM】16位 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 94K |
| 代理商： | BR93LC46-W |
BR93LC46-W / BR93LC46F-W / BR93LC46RF-W /
Memory ICs
BR93LC46FJ-W / BR93LC46RFJ-W / BR93LC46FV-W
(3) Timing chart
CS
SK
DI
DO (READ)
DO (WRITE)
STATUS VALID
t
DF
t
DF
t
PD1
t
PD0
t
DIH
t
DIS
t
CSS
t
CSH
t
SKH
t
SKL
Fig.9 Synchronized data timing
·
Data is acquired from DI in synchronization with the SK rise.
·
During a reading operation, data is output from DO in synchronization with the SK rise.
·
During a writing operation, a Status Valid (READY or BUSY) is valid from the time CS is HIGH until time tCS after CS falls following the input of
a write command and before the output of the next command start bit. Also, DO must be in a HIGH-Z state when CS is LOW.
·
After the completion of each mode, make sure that CS is set to LOW, to reset the internal circuit, before changing modes.
(4) Reading (Fig.10)
When the read command is acknowledged, the data (16 bits) for the input address is output serially. The data is
synchronized with the SK rise during A0 acquisition and a “0” (dummy bit) is output. All further data is output in
synchronization with the SK pulse rises.
CS
SK
DI
DO
(
1)
(
2)
D14
D15
D1
D14
D15
0
High Z
1
1
0
A5
A4
A1
A0
1
2
4
9
10
25
26
D0
(
2) Address auto increment function: These ICs are equipped with an address auto increment function which is effective only during reading operations. With
this function, if the SK clock is input following execution of one of the above reading commands, data is read from upper addresses in succession.
CS is held in HIGH state during automatic incrementing.
(
1) If the first data input following the rise of the start bit CS is "1", the start bit is acknowledged. Also, if a "1" is input following several zeroes in succession, the
"1" is recognized as the start bit, and subsequent operation commences. This applies also to all commands described subsequently.
Fig.10 Read cycle timing (READ)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BR93LC46F-W | 64】16bits serial EEPROM |
| BR93LC46FJ-W | 64】16bits serial EEPROM |
| BR93LC46RFJ-W | 64】16bits serial EEPROM |
| BRT1A | Quad Differential Receivers(四差分接收器) |
| BRF1A | Quad Differential Receivers(四差分接收器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BR93LC56 | 制造商:ROHM 制造商全稱:Rohm 功能描述:2,048-Bit Serial Electrically Erasable PROM |
| BR93LC56A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microwire Serial EEPROM |
| BR93LC56AF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microwire Serial EEPROM |
| BR93LC56F | 制造商:ROHM 制造商全稱:Rohm 功能描述:2,048-Bit Serial Electrically Erasable PROM |
| BR93LC56FJ-W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microwire Serial EEPROM |
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